High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator

You can simulate your HBM2 EMIF IP using the Cadence* Xcelium Parallel Simulator.
  1. Navigate to: project <hbm_fp_0_example_design>/sim/ed_sim/xcelium.
  2. Type sh xcelium_setup.sh to run the simulation.