High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor

You can use the Performance Monitor to check the performance metrics of each pesudo-channel or all eight channels.

To enable the Performance Monitor, select Enable Performance Monitoring on the Example Designs tab in the HBM2E parameter editor.

  1. Click Tools > System Debugging Tools > System Console to open the System Console.
  2. Load the ed_synth.sof file into the System Console by clicking File > Load Design > ed_synth.sof. (Alternatively, you can load the .sof file from the terminal command line, if you prefer not to use the System Console.)
  3. After you have loaded the ed_synth.sof file, access the testengine_library.tcl file by entering the following command in the System Console:
    source hydra_sw/testengine_library.tcl
    You can see the test engine library loaded now. The testengine_library.tcl file includes the functions to interact with the test engine IP on hardware over a JTAG connection.
  4. Load the pmon_library.tcl file in system-console by entering the following command:
    source pmon_library.tcl
  5. Set the metric configuration on desired AXI4 performance monitors:
    pmon_set_all {config}
  6. Clear the counters and internal state of all performance monitors by typing the following command:
  7. Reset and program a new traffic pattern by typing:
  8. Run traffic over the interface by typing:
  9. Read the metrics on the AXI4 performance monitor by typing:

The above steps are a recommended sequence of function calls to configure the Performance Monitor. For additional information on performance monitor functions available for your testing, refer to the pmon_library.tcl file.

The performance monitor reports the metrics measured at the Test Engine IP's AXI4 manager interface, and not at the memory interface.