High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project

This topic outlines the flow for simulating the HBM2E IP instantiated in your project, rather than the HBM2E design example.
  1. In your simulation project, include <project_directory>\<IP_name>\sim\<IP_name>.v
  2. The generated HBM2E IP simulation file set does not include an HBM2E memory model file; you must add a memory model file to the project. Intel® recommends that you use the memory model from the design example simulation file set generated from your IP: hbm_fp_0_example_design\sim\ip\ed_sim\ed_sim_hbm_fp_0\hbm_arch_fp_10\sim\altera_hbm2e_model.sv
  3. The HBM2E IP netlist does not include the mapping for the NoC initiators-targets connectivity, and the address mapping. You must add the RTL registration statements in the top-level of your design for simulating your HBM2E IP. You can refer to the registration statements included in the ed_sim.v file generated with the design example.