High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description

The HBM2E design example demonstrates the basic functions of the IP. The design performs successful read and write requests from user logic to the HBM2E DRAM memory, though the HBM2E IP.

You can specify the parameter settings of your choice and generate the design example from the Example Design tab in the IP parameter editor.