High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation

The following illustration shows a high-level block diagram of the HBM2E example design that provides the simulation environment for the HBM2E IP when generated for simulation.
Figure 4. High Bandwidth Memory (HBM2E) Interface FPGA IP Generated for Simulation

The Traffic Generator emulates a real-world application that writes to, and reads back from memory and validates the read data. You can modify the traffic generator traffic pattern or drive the transactions to the HBM2E memory with your own logic.

Simulation incorporates abstract models of the NoC and HBM2E memory device. The hardened HBM2E controller is simulated in full, and simulation of the UIB is simplified by omitting the calibration phase. The HBM2E controller converts AXI memory access commands to HBM commands. The universal interface block PHY (UIB PHY) is the physical-layer interface that carries low-level signaling between the controller and HBM2E device.

The HBM2E Model is an abstract generic model representative of the HBM2E DRAM for simulation. This is not a vendor-specific model.