High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation

When you compile the AXI4-Lite-enabled design example, the test engine IP configures the fixed traffic pattern for the AXI4-Lite driver.

You cannot change or modify the traffic pattern for the AXI4-Lite driver.

The design example does not generate any AXI4-Lite driver in this directory, however it sets the 0th number of driver as the default AXI4-Lite driver; hence in this type of design you see only main-band drivers in the design example directory.

When you run the AXI4-Lite-enabled design in simulation, you see the passing status for driver 0, which is the AXI4-Lite specific driver. The current release of the IP is limited, insofar as you cannot check the driver status for the AXI4-lite driver on hardware; however, you can use the AXI4-Lite driver register space to communicate with the Universal Interface Block (UIB) MMR.