High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

ID 773266
Date 4/29/2024
Document Table of Contents

3.2.1. Initiator to Target NoC Mapping

This topic describes the configurations of the design example.

Use case 1: 1 × 1 Full Address Connection

In this configuration each pair of initiator and target is directly mapped. As shown in the figure below, the CH0 PC0 channel of the HBM controller connects to target 0 which connects to initiator 0.

Figure 6. 1 × 1 Full Address Connection

The table below illustrates the mapping of HBM2E controller pseudo-channels to HBM2E DRAM channels to targets and HBM2E DRAM channels.

Table 3.  Channel Mapping
HBM2E IP GUI Channel AXI4 Channel (HBMC) HBM2E DRAM Channel
Channel 0 ch0_u0 Channel E
Channel 1 ch1_u0 Channel F
Channel 2 ch2_u0 Channel A
Channel 3 ch3_u0 Channel B
Channel 4 ch4_u0 Channel G
Channel 5 ch5_u0 Channel H
Channel 6 ch6_u0 Channel C
Channel 7 ch7_u0 Channel D

Use case 2: 16 × 16 Cross Bar Connection

In this configuration the address map of each initiator is configured to allow it to drive traffic to all of the 16 targets. You can use this design example configuration as a starting point for designs that have multiple masters accessing the same HBM2E pseudo-channels, for example when there is ping-pong buffering.

Note: You cannot choose this configuration if you generate the design example with fewer than 8 channels enabled.

The design example offers options to use the AXI4-Lite access and fabric NoC with each of the NoC connectivity configurations.