Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 9/11/2023

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Document Table of Contents

2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check

  • Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in rows along the top periphery and bottom periphery of the device. Each I/O bank has two sub-banks. Each sub-bank has its own PLL, DPA and SERDES circuitries, and individual VCCIO_PIO voltage rail.
  • Ensure that the selected I/O standard is supported in the targeted I/O sub-bank.
  • Place I/O pins that share the same VCCIO_PIO voltage levels in the same I/O sub-bank.
  • Verify that all output signals in each I/O sub-bank are intended to drive out at the sub-bank's I/O voltage level.
  • Verify that all voltage-referenced signals in each I/O lane are intended to use the same VREF source by adhering to the voltage-referenced input standards grouping per I/O lane.