Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 9/11/2023

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Document Table of Contents

2.2. GPIO-B Features

The I/O bank within the GPIO-B interface supports various differential and single-ended I/O standards to cater to different types of interfacing requirements.
  • Single-ended LVCMOS for general purpose I/O interfacing.
  • Single-ended and pseudo-differential voltage-referenced I/O standards for general purpose and external memory interfacing. The differential voltage-referenced output pins are not true differential output pins. The differential voltage-referenced I/O standards use two single-ended output pins with one of the output pins inverted.
  • True differential I/O buffer pairs using the True Differential Signaling and SLVS-400 I/O standards. The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true differential buffer pair forms a true differential channel.

Power Pins for the GPIO-B Buffers

The VCCIO_PIO and VCCPT pins power the I/O buffers located in the I/O bank within the GPIO-B interface.

GPIO-B Buffer Features

  • Single-ended non-voltage referenced and voltage-referenced I/O standards
  • Differential voltage-referenced I/O standards
  • True differential transmitters and receivers
  • Serializer/deserializer (SERDES)
  • Programmable slew rate
  • Programmable weak pull-up resistor
  • Programmable differential output voltage (VOD) for true differential output buffers
  • Programmable receiver equalization calibration
  • On-chip series termination (RS OCT)
  • On-chip parallel termination (RT OCT)
  • On-chip differential termination (RD OCT)
  • Dynamic on-chip parallel termination
  • Internally generated VREF
  • Programmable pre-emphasis for true differential output buffer
  • Programmable de-emphasis