2.1. GPIO-B Bank Overview
- Top index sub-bank—the pin index numbers are 48 to 95.
- Bottom index sub-bank—the pin index numbers are 0 to 47.
Each sub-bank contains four I/O lanes. Each I/O lane has 12 I/O pins. Consequently, there are a total of 48 single-ended I/O pins or 24 true differential I/O pairs in each sub-bank.
If you use SERDES, you can configure each I/O lane to support a SERDES transmitter or receiver channel, with optional dynamic phase alignment (DPA), for:
- Up to six dedicated differential receiver input buffer pairs
- Up to six dedicated differential transmitter output buffer pairs
If you do not use SERDES, you can configure each true differential buffer as receiver or transmitter.
Additionally, each sub-bank also contains dedicated circuitries including:
- I/O PLL
- Hard memory controller
- On-chip termination (OCT) calibration blocks
The total number of GPIO-B banks varies across different device packages. Some GPIO-B banks are shared with the SDM and HPS function blocks. Refer to the device pin-out files for available I/O banks for each device package.