Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

ID 772138
Date 9/11/2023

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Document Table of Contents

6.5. GPIO Intel® FPGA IP Architecture

The GPIO IP supports the GPIO-B components and features of the M-Series devices. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP.

Components of the GPIO IP:

  • Double data rate input/output (DDIO)—doubles the data-rate of a communication channel
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
  • I/O buffers—connect the pads to the FPGA