MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023

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Document Table of Contents

5.1. System Register Map

Refer to the respective IP/subsystem documentation for internal address offsets. At the system level, BAR2 of each PF drive the downstream CSR space through the MCDMA PIO interface. Registers inside MCDMA are targeted to BAR0 of each PF for Queue control (D2H and H2D directions) and MSI-X table updates. General CSR (GCSR) of MCDMA is only maintained by PF0-BAR0.

The PIO address is arranged as {vf_active,clog2(PF_NUM),clog2(VF_NUM),PIO BAR2 Address} where vf_active, clog2(PF_NUM) and clog2(VF_NUM) are declared as 1-bit each since we support only 2 PFs and no VFs. Each PF’s BAR2 can be enabled for 32MB i.e. 26-bit interface and the upper address bits differentiate the addressing between 2 PFs. The PIO interface is accessible irrespective of configuring the datapath queues. Since this design does not support any VFs, vf address bits are removed from AVMM address using BAR interpreter logic which reduces the needed address range for design.

This path supports 64-bit register access as well as 32-bit register access with adapters in the path. Port MUX/DeMUX/Crypto interfaces all are 32-bit accesses. The current MACsec IP does not support these interfaces but it is under evaluation to expose them in the future.
Figure 30. Address Map from MCDMA PIO Interface