MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023
Public

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7. Generating the System Design

This chapter discusses how to obtain, simulate, build, and run the System Design on hardware. The design supports different flavors of Tile combinations with different data rate support. The design is flexible enough to be configured for an E-Tile or an F-Tile based MAC with 25G or 100G data rate support using compile time directives as shown in the sections below.