MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023

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Document Table of Contents

2.6.1. MCDMA MSI-X Table Configuration

The MCDMA comes with its own memory offset space for MSI-X Table and PBA Table for each function enabled. It is always tied to the BAR0 address space of each function. Settings like Table BIR/PBA BIR and Table Offset/PBA Offset are not valid. As shown below, the MSI-X Table starts at 0x10_0000 offset on each function’s BAR0 with maximum size allocated of 512KB (but requires only 32KB to support maximum 2048 MSI-X vectors as per spec.). The PBA Table starts at offset of 0x18_0000 on each function’s BAR0.
Table 3.  MCDMA Address Space
Address Space Name Range Size Description
QCSR (D2H, H2D) 22'h00_0000 - 22'h0F_FFFF 1MB Individual queue control registers. Up to 2048 D2H and 2048 H2D queues.
MSI-X (Table and PBA) 22'h10_0000 - 22'h1F_FFFF 1MB MSI-X Table and PBA space.
GCSR 22'h20_0000 - 22'h2F_FFFF 1MB General DMA control and status registers.
Reserved 22'h30_0000 - 22'h3F_FFFF 1MB Reserved.
The current solution supports only 4 MSI-X vectors per PF, out of it 2 are dedicated for the MCDMA internal use. The table below gives the exact offsets for each usage per PF.
Table 4.  Address Offsets Per PF
Address Offset Usage Description
BAR0 + 0x10_0000 + 0x00 H2D DMA Vector DMA Internal Use for H2D descriptor updates
BAR0 + 0x10_0000 + 0x10 H2D Event Interrupt Reserved
BAR0 + 0x10_0000 + 0x20 H2D DMA Vector DMA Internal Use for D2H descriptor updates
BAR0 + 0x10_0000 + 0x30 H2D Event Interrupt MACSec Interrupt