MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023

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Document Table of Contents

7.11. Building the Hardware Design

The hardware design is built using the Quartus software. The design goes through various steps beginning at RTL design, then going through synthesis, fitter stages, and SOF generation. Follow the steps below to build the hardware design.

  1. Navigate to the env/ directory.
  2. Source the environment settings. This is to be done only once in a shell.

    -- source

  3. Navigate up one directory to the syn/ subdirectory.
  4. Enter the following command to update the .qsf file.
    • For E-Tile designs:
      1. For 25G: sh agx_wr_mudv/ agx_wr_mudv 25G
      2. For 100G: sh_agx_wr_mudv/ agx_wr_mudv 100G
    • For F-Tile designs:
      1. For 25G: sh agx_nr_mudv/ agx_nr_mudv 25G
      2. For 100g: sh agx_nr_mudv/ agx_nr_mudv 100G
  5. Run the make command to execute the build steps.
    • For F-Tile designs, use agx_nr_mudv in the below commands. For E-tile designs, use agx_wr_mudv.
      1. Run this command to execute clean, setup, synthesis & fitter steps:

        make build TARGET=agx_nr_mudv

      2. Run this command to open the project in gui:

        make gui TARGET=agx_nr_mudv

      3. Run this command to clean the previous results:

        make clean TARGET=agx_nr_mudv

      4. Run this command to execute only the synthesis stage:

        make clean setup synth TARGET=agx_nr_mudv

      5. Run this command to execute only the fitter stage, provided all the synth outputs are present already:

        make fit TARGET=agx_nr_mudv

Note: Quartus run is generated under the $SRD_ROOTDIR/syn/<TARGET>/output_files after every run.