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Ixiasoft
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Ixiasoft
7.9. Running UVM Simulation
Follow these steps to run Synopsys UVM simulation. These steps are only applicable if your Synopsys simulator supports UVM simulation.
- Before running the steps below, you must follow steps 1-4 of the Running Verilog Simulation section.
- Go to $SRD_ROOTDIR/verification/testbench.
- Run the makefile for your corresponding design.
- For E-tile: make -f Makefile.mk cmplib
- For F-tile: make -f Makefile.mk cmplib MACSEC_SRD_FTILE=1
- Run the following simulation command for your corresponding design. The simulation is run using a Makefile. Refer to the following for some example commands and explanation of Makefile targets, options, and behaviors.
Example commands:
- For E-tile:
- To build and run in a single step for a 25G design:
make -f Makefile.mk build run TESTNAME=macsec_srd_csr_hw_rst_test DUMP=1 25G=1
- To build and run in a single step for a 100G design:
make -f Makefile.mk build ru TESTNAME=macsec_srd_csr_hw_rst_test DUMP=1
- To build and run in a single step for a 25G design:
- For F-tile:
- To build and run in a single step for a 25G design:
make -f Makefile.mk build run TESTNAME=macsec_srd_csr_hw_rst_test DUMP=1 25G=1 MACSEC_SRD_FTILE=1
- To build and run in a single step for a 100G design:
make -f Makefile.mk build ru TESTNAME=macsec_srd_csr_hw_rst_test DUMP=1 MACSEC_SRD_FTILE=1
- To build and run in a single step for a 25G design:
Makefile Tasks | Options |
---|---|
Makefile targets for running tests |
|
Makefile target options |
|
Running build and make targets in a single step with DUMP=1 enables waveform dump generation.
make -f Makefile.mk build DUMP=1 25G=1 make -f Makefile.mk run TESTNAME=macsec_srd_csr_hw_rst_test
You can also add DUMP=1 to run target if you desire waveform dumping.