MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents GLOBAL Reset

Two functionalities supported in reset are listed below:
  • The MACsec IP is reset through the subsystem_cold_rst_n assertion/deassertion. There are 2 additional resets, app_ip_lite_areset_n and app_ip_st_areset_n, which can be triggered to reset the CSR block and the remaining logic blocks respectively. A programmable counter counts down upon the subsystem_cold_rst_n assertion/deassertion and assert/deassert subsystem_cold_rst_ack_n when the counter = 0.
  • The MACsec IP implements a software reset in the CSR register. The software resets the core logic, leaving the configuration registers unchanged. The MACsec IP is in the reset state if the CSR bit is set to 0. While in this state, no traffic is allowed in either the MACsec IP direction. The GLOBAL_SW_RESET register is used to reset the software.