MACsec Intel FPGA System Design User Guide

ID 767516
Date 6/26/2023

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3.2. Resets

The system reset for PCI Express (pin_perst_n) driven by the downstream port through the edge connector is the only hard reset available to the entire design. This reset is provided as an output by the endpoint core which is connected to the MCDMA.

In addition, a software driver programmed reset (soft rest), called app_rst_n, is provided by the MCDMA (SW_RESET register[0]) which resets MCDMA soft IP blocks as well as the user logic. This is allowed to be driven by PF0 only. The soft reset feature is used when a driver is loading and unloading to flush out all pending transactions and prevent any stale transactions from interrupting the host when the hardware is not in use.
Figure 29. Reset Tree