Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 12/11/2023
Document Table of Contents

4.3.3. Soft-CDR Mode

The F-Series and I-Series SERDES channel offers the soft-CDR mode to support the GbE and SGMII protocols. A receiver PLL uses the local clock source for reference.
Figure 21. Receiver Data Path Block Diagram—Soft-CDR Mode

In the soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock phase to sample the data. The receiver uses the selected clock for bit slip operation and deserialization.

Additionally, the DPA block divides the selected DPA clock by the deserialization factor and forwards it as rx_divfwdclk together with the deserialized data to the FPGA fabric. The rx_divfwdclk clock signal resides in the periphery clock (PCLK) network.

If you use the soft-CDR mode, do not assert the rx_dpa_reset signal after the DPA has been trained. The DPA continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between the reference clock and incoming data.

In the soft-CDR mode, the rx_dpa_locked signal is invalid because the DPA continuously changes its phase to track PPM differences between the upstream transmitter and the local receiver input reference clocks. However, you can use the rx_dpa_locked signal to determine the initial DPA locking conditions that indicate the DPA has selected the optimal phase tap to capture the data. The rx_dpa_locked signal deasserts when the receiver operates in the soft-CDR mode. The receiver also forwards the rx_divfwclk parallel clock, generated from the DPA clock, to the FPGA fabric.

Note: In the soft-CDR mode, you must place all receiver channels of a SERDES instance in one I/O sub-bank. Refer to the related information for the number of soft-CDR channels supported in each sub-bank. Refer to device pin-out files to identify the locations pin locations that support the soft-CDR mode.