Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 12/11/2023
Document Table of Contents

4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver

The F-Series and I-Series LVDS SERDES receivers are dedicated circuitries.

Each dedicated receiver circuitry consists of:

  • A true differential buffer
  • A deserializer
  • I/O PLLs that you can share between the SERDES transmitter and receiver
  • A data realignment block (bit slip)
  • A data phase alignment (DPA) block
  • A synchronizer
Dedicated Circuitry and Features of the LVDS SERDES Receiver
Dedicated Circuitry / Feature Description
Differential I/O buffer

Supports True Differential Signaling I/O standard, which is compatible with LVDS, RSDS, Mini-LVDS, and LVPECL

SERDES Up to 10-bit wide deserializer
Phase-locked loops (PLLs) Generates different phases of a clock for data synchronizer
Data realignment (bit slip) Inserts bit latencies into serial data
Dynamic phase alignment (DPA) Chooses a phase closest to the phase of the serial data
Synchronizer (FIFO buffer) Compensate for phase differences between the data and the receiver’s input reference clock
Skew adjustment Manual
On-chip termination (OCT) 100 Ω in True Differential Signaling I/O standards