Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 12/11/2023
Document Table of Contents

4.3.1. Non-DPA Mode

The non-DPA mode disables the DPA and synchronizer blocks. The receiver registers the input serial data at the rising edge of the serial fast_clock clock.

The I/O PLL generates the fast_clock clock signal. The fast_clock signal clocks the data realignment and deserializer blocks.

Figure 19. Receiver Data Path Block Diagram—Non-DPA Mode