Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 12/11/2023
Document Table of Contents

2.1. F-Series and I-Series GPIO Banks, SERDES, and DPA Locations

The GPIO banks are located at the top and bottom I/O bank rows.
Figure 1.  GPIO Bank Structure (Die Top View)This figure shows the GPIO bank structure of F-Series and I-Series devices. The figure shows the view of the die as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View". Different device packages have different number of GPIO banks. Refer to the device pin-out files for available GPIO banks and the locations of the SDM shared and HPS shared GPIO banks for each device package.