Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

ID 721819
Date 12/11/2023
Document Table of Contents

4.2. Clocking the LVDS SERDES Receivers

The I/O PLL receives the external clock input and generates different phases of the same clock. The DPA block automatically selects one of the clocks from the I/O PLL and aligns the incoming data on each channel.

The synchronizer circuit compensates for any phase difference between the DPA clock and the data realignment block. When necessary, the data realignment circuitry, which you control, inserts a single or multiple bits of latency in the serial bit stream to align the data to the word boundary.

The physical medium connecting the transmitter and receiver SERDES channels may introduce skew between the serial data and the source-synchronous clock. The instantaneous skew between each SERDES channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver.

The different modes provide different options to compensate the skew between the source synchronous or reference clock, and the serial data:

  • Non-DPA mode—you can statically select the optimal phase between the source synchronous clock and the received serial data.
  • DPA mode—the DPA circuitry automatically selects the best phase between the source synchronous clock and the received serial data.
  • Soft-CDR mode—provides opportunities for synchronous and asynchronous applications for chip-to-chip and short reach board-to-board applications for SGMII protocols.
Note: Only the non-DPA mode requires manual skew adjustment.