Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

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ID 721819
Date 12/11/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview 2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture 3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter 4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver 5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide 6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing 7. LVDS SERDES Intel® FPGA IP Design Examples 8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines 9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines 10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series 11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview x
1.1. LVDS SERDES Usage Modes
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture x
2.1. F-Series and I-Series GPIO Banks, SERDES, and DPA Locations 2.2. SERDES Blocks, Modes, and Clock Domains
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter x
3.1. LVDS SERDES Transmitter Blocks 3.2. Serializer 3.3. Differential I/O Bit Position 3.4. Clocking the Differential Transmitters
3.2. Serializer x
3.2.1. Serializer Bypass for DDR and SDR Operations
3.4. Clocking the Differential Transmitters x
3.4.1. Transmitter Output Clock Parameters Settings
3.4.1. Transmitter Output Clock Parameters Settings x
3.4.1.1. Edge-Aligned tx_outclock to tx_out 3.4.1.2. Center-Aligned tx_outclock to tx_out
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver x
4.1. LVDS SERDES Receiver Blocks 4.2. Clocking the LVDS SERDES Receivers 4.3. LVDS SERDES Receiver Modes
4.1. LVDS SERDES Receiver Blocks x
4.1.1. Dynamic Phase Alignment Block 4.1.2. Synchronizer (DPA FIFO) 4.1.3. Data Realignment Block (Bit Slip) 4.1.4. Deserializer
4.2. Clocking the LVDS SERDES Receivers x
4.2.1. Receiver Input Clock Parameters Settings
4.2.1. Receiver Input Clock Parameters Settings x
4.2.1.1. Edge-Aligned inclock to rx_in 4.2.1.2. Center-Aligned inclock to rx_in
4.3. LVDS SERDES Receiver Modes x
4.3.1. Non-DPA Mode 4.3.2. DPA Mode 4.3.3. Soft-CDR Mode
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide x
5.1. LVDS SERDES Intel® FPGA IP 5.2. LVDS Interface with External PLL Mode 5.3. LVDS SERDES IP Initialization and Reset
5.1. LVDS SERDES Intel® FPGA IP x
5.1.1. Release Information 5.1.2. LVDS SERDES Intel® FPGA IP Features 5.1.3. LVDS SERDES IP Usage Modes 5.1.4. Generating the LVDS SERDES Intel® FPGA IP 5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings 5.1.6. LVDS SERDES Intel® FPGA IP Signals
5.1.4. Generating the LVDS SERDES Intel® FPGA IP x
5.1.4.1. Intel® FPGA IP Generation Output
5.1.5. LVDS SERDES Intel® FPGA IP Parameter Settings x
5.1.5.1. LVDS SERDES Intel® FPGA IP General Settings 5.1.5.2. LVDS SERDES Intel® FPGA IP PLL Settings 5.1.5.3. LVDS SERDES Intel® FPGA IP Receiver Settings 5.1.5.4. LVDS SERDES Intel® FPGA IP Transmitter Settings 5.1.5.5. LVDS SERDES Intel® FPGA IP Clock Resource Summary
5.2. LVDS Interface with External PLL Mode x
5.2.1. IOPLL IP Signal Interface with LVDS SERDES IP 5.2.2. IOPLL Parameter Values for External PLL Mode 5.2.3. Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode
5.3. LVDS SERDES IP Initialization and Reset x
5.3.1. Initializing the LVDS SERDES IP in Non-DPA Mode 5.3.2. Initializing the LVDS SERDES IP in DPA Mode 5.3.3. Resetting the DPA 5.3.4. Word Boundaries Alignment
5.3.4. Word Boundaries Alignment x
5.3.4.1. Aligning Word Boundaries
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing x
6.1. LVDS SERDES Intel® FPGA IP Timing 6.2. LVDS SERDES Source-Synchronous Timing Budget
6.1. LVDS SERDES Intel® FPGA IP Timing x
6.1.1. I/O Timing Analysis 6.1.2. FPGA Timing Analysis 6.1.3. Timing Analysis for the External PLL Mode
6.1.1. I/O Timing Analysis x
6.1.1.1. Obtaining RSKM Report 6.1.1.2. Obtaining TCCS Report
6.2. LVDS SERDES Source-Synchronous Timing Budget x
6.2.1. Transmitter Channel-to-Channel Skew 6.2.2. Receiver Skew Margin
7. LVDS SERDES Intel® FPGA IP Design Examples x
7.1. LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples 7.2. LVDS SERDES IP Simulation Design Example
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines x
8.1. Use PLLs in Integer PLL Mode for LVDS 8.2. Use High-Speed Clock from PLL to Clock SERDES Only 8.3. Pin Placement for Differential Channels 8.4. SERDES Pin Pairs for Soft-CDR Mode 8.5. Placing LVDS Transmitters and Receivers in the Same GPIO Bank
1. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Overview
2. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Architecture
3. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Transmitter
4. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Receiver
5. Intel Agilex® 7 F-Series and I-Series High-Speed LVDS I/O Implementation Guide
6. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Timing
7. LVDS SERDES Intel® FPGA IP Design Examples
8. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Design Guidelines
9. Intel Agilex® 7 F-Series and I-Series LVDS SERDES Troubleshooting Guidelines
10. Documentation Related to the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series
11. Document Revision History for the Intel Agilex® 7 LVDS SERDES User Guide: F-Series and I-Series

5.2.2. IOPLL Parameter Values for External PLL Mode

These examples show the clocking requirements to generate output clocks for LVDS SERDES IP using the IOPLL IP. The examples set the phase shift with the assumption that the clock and data are edge-aligned at the pins of the device.
Note: For other clock and data phase relationships, Intel recommends that you first instantiate your LVDS SERDES IP interface without using the external PLL mode option. Compile the IPs in the Intel® Quartus® Prime software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the IOPLL IP parameter editor and then connect the appropriate output to the LVDS SERDES IPs.
Table 28.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate three output clocks using an IOPLL IP if you are using the non-DPA receiver.
Parameter

outclk0

(Connects as lvds_clk[0] to the ext_fclk port of LVDS SERDES IP transmitter or receiver)

outclk1

(Connects as loaden[0] to the ext_loaden port of LVDS SERDES IP transmitter or receiver)

outclk4

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

Duty cycle

50%

 100/serialization factor

50%

The calculations for phase shift, using the RSKM equation, assume that the input clock and serial data are edge aligned. Introducing a phase shift of 180° to sampling clock (outclk0) ensures that the input data is center-aligned with respect to the outclk0, as shown in the following figure.

Figure 24. Phase Relationship for External PLL Interface Signals


Table 29.  Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode)This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate four output clocks using an IOPLL IP if you are using the DPA or soft-CDR receiver.
Parameter

outclk0

(Connects as lvds_clk[1:0] to the ext_lvds_clk[1:0] ports of LVDS SERDES IP transmitter or receiver)

outclk1

(Connects as loaden[1:0] to the ext_loaden[1:0] ports of LVDS SERDES IP transmitter or receiver)

Not required for the soft-CDR receiver.

outclk4

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] port of LVDS SERDES IP)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

Use the value recommended by the LVDS and IOPLL IPs
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

—
Duty cycle

50%

 100/serialization factor

50%

—
Table 30.   Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter and Receiver Channels (Receiver in DPA or Soft-CDR Mode) This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate six output clocks using an IOPLL IP. Use these settings if you use transmitter channels shared with receiver channels in DPA or soft-CDR mode.
Parameter

outclk0

(Connects as lvds_clk[1:0] to the ext_lvds_clk[1:0] ports of LVDS SERDES IP receiver)

outclk1

(Connects as loaden[1:0] to the ext_loaden[1:0] ports of LVDS SERDES IP receiver)

Not required for the soft-CDR receiver.

outclk4

(Used as the core clock for the parallel data registers for both transmitter and receiver, and connects to the ext_coreclock port of LVDS SERDES IP)

VCO Frequency

(Connects as phout[7:0] to the ext_vcoph[7:0] ports of LVDS SERDES IP)

outclk2

(Connects as lvds_clk[1:0] to the ext_lvds_clk[1:0] ports of LVDS SERDES IP transmitter)

outclk3

(Connects as loaden[1:0] to the ext_loaden[1:0] ports of LVDS SERDES IP transmitter)

Frequency

data rate

data rate/serialization factor

data rate/serialization factor

data rate
Phase shift

180°

[(deserialization factor – 1)/deserialization factor] × 360°

180/serialization factor

(outclk0 phase shift divided by the serialization factor)

—
Duty cycle

50%

 100/serialization factor

50%

—
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