F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 4/04/2022

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1.3. Simulating the Design

Figure 5. Simulating the Design flow

To run example design simulation, follow these steps:

  1. Generate the necessary simulation setup files.
    1. Using GUI method:
      1. Open the Intel® Quartus® Prime Project in Intel® Quartus® Prime directory.
      2. Run Support-Logic Generation to generate the transceiver RTL files.
        Figure 6. Support-Logic Generation in Compilation Dashboard

      3. To generate the simulation setup files, click Tools > Generate Simulator Setup Script for IP....
      4. Set the output directory to .../simulation.
        Figure 7. Generating Simulation Setup File Using GUI
    2. Using command-line:
      1. Open a command-line terminal.
      2. Make sure your environment variable (QUARTUS_ROOTDIR) points to the bin/bin64 in your Intel® Quartus® Prime installation directory
      3. Change the current directory to the generated simulation folder in your terminal.
      4. Run this command source sim_setup_gen.sh.
  2. Go to simulation folder.
  3. Go to the desired simulator folder and run the simulation script:
    1. ModelSim* SE or Questa* FE: Bring up the simulator GUI, change directory to mentor folder and type do mentor.do
    2. VCS* : Go to synopsys/vcs folder and type source vcs_sim.sh.
    3. VCS* MX : Go to synopsys/vcsmx folder and type source vcsmx_sim.sh
    4. Xcelium* : Go to xcelium folder and type source xcelium_sim.sh
  4. A successful simulation ends with the following message: