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1.5. Design Example Parameters
Select available design example to be generated.
|Dynamic TX clock Switching||
Turns on this option to allow dynamic switching between 1 and 1/1.001 data rates. Tx reference clock switching requires two reference clocks for TX PLL.
Note: TX PLL reference clock switching is only available when you select Serial Loopback design.
|Simulation||On / Off||Turns on this option to generate necessary files for simulation testbench.|
Turns on this option to generate necessary files for Intel® Quartus® Prime compilation and hardware demo.
This option is greyed out and set to always Enabled. This is because synthesis files are still required to run Support-Logic Generation stage in Intel® Quartus® Prime to generate the transceiver tile’s files which are essential to run simulation as well.
|Generate File Format||
||Select the HDL format for generated design example fileset. Note that the HDL format only affects the generated top level IP files. All the other files, for example testbenches and top level files for hardware demo are in Verilog.|
|Select Daughter card||
Select the daughter card for the targeted design example. This option is greyed out as only Nextera VIDIO 12G-SDI FMC card is supported in this design example.
Select the board for the targeted design example.
|Change Target Device||On / Off||
Turn on this option and select the preferred device variant for the development kit.
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