F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 4/04/2022

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1.2. Generating the Design

Configure the SDI II Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.
Figure 3. Generating the Design Flow
  1. Create an empty project targeting Intel® Agilex™ F-tile device family and select the desired device.
  2. In the IP Catalog, locate and double-click SDI II Intel FPGA IP. The IP Parameter Editor window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, select your desired IP settings. The generated design example is based on your settings.
  6. On the Design Example tab, select the desired parameter for the design example. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
  7. For Target Development Kit, select the relevant FPGA development kit. You may change the target device using the Change Target Device parameter if your board revision does not match the grade of the default targeted device.
  8. Click Generate Example Design button to initiate the design generation.
Figure 4. Design Example Tab in SDI II IP Parameter Editor