F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 4/04/2022
Public

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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.04.04 22.1 19.2.1
  • Changed the title from F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide to F-Tile SDI II Intel FPGA IP Design Example User Guide.
  • Added files to Directory Structure for the Design Examples Figure and Other Generated Files in RTL Folder Table.
  • Removed Supported Verilog only from the following sections:
    • Simulating the Design
    • Hardware and Software Requirements
  • Added steps in Compiling and Testing the Design in Hardware.
  • Added Dynamic TX clock Switching parameters in Parameters available in Design Example tab Table.
  • Added Parallel loopback without external VCXO in Design Example Detailed Description.
  • Edited Intel® Quartus® Prime software version in Hardware and Software Requirements
  • Added DR Arbiter and DR IP to the following Figures:
    • Components required for TX and RX only design on Intel Agilex Device
    • Parallel loopback with simplex mode
    • Parallel loopback with duplex mode
    • Serial loopback with simplex mode
    • Serial loopback with duplex mode
  • Added new components to the following Tables:
    • Device Under Test (DUT) Components.
    • Loopback Top Components
    • Clocking Scheme Component
    • Top Level Signals
    • RX top/ TX top/ Du top parameters
    • RX top/ TX top/ Du top signals
    • Loopback top signals
  • Added triple-rate and multi-rate design in Test Description.
2022.01.28 21.4 19.2.0 Initial release.
Level Two Title