F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 4/04/2022
Public

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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

2.3. Functional Description

The SDI II Intel® FPGA IP core design example supports the following simplex and duplex transceiver mode:.
  • Parallel loopback with simplex mode
  • Parallel loopback with duplex mode
  • Serial loopback with simplex mode
  • Serial loopback with duplex mode
Figure 13. Parallel Loopback with Simplex Mode
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Multiple copies of block are required for different PHY profiles in triple rate/multi rate designs.
  • (3)Block/Connection only required for parallel loopback without external VCXO designs.
Figure 14. Parallel Loopback with Duplex Mode
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Multiple copies of block are required for different PHY profiles in triple rate/multi rate designs.
  • (3)Block/Connection only required for parallel loopback without external VCXO designs.
Figure 15. Serial Loopback with Simplex Mode
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs.
  • (2)Multiple copies of block are required for different PHY profiles in triple rate/multi rate designs.
Figure 16. Serial Loopback with Duplex Mode
Note:
  • Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
  • (1)Block/Connection only required for triple rate/multi rate designs. Multiple copies of Rx PHY IP are required for different PHY profiles in triple rate/multi rate designs.
  • (2)Block/Connection only required for for Tx PLL reference clock switching designs. Multiple copies of Tx PHY IP are required for both reference clock profiles.
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