A newer version of this document is available. Customers should click here to go to the newest version.
2.3.1. Design Components
The SDI II Intel FPGA IP core design examples require the following components.
|F-tile PMA/FEC Direct PHY||
Note: For triple-rate or multi-rate mode design, you see multiple copies of this IP which representing different reconfiguration profile.
|SDI RX DR-F Mgmt||
|SDI TX DR-F Mgmt||
Adapter block which includes DCFIFO for converting the bit width of parallel data between transceiver and SDI core, as well as to transfer the data between these two clock domains.
|Loopback FIFO||This module contains DCFIFO for video data transferring between receiver clock domain and transmitter clock domain.|
|Video Pattern Generator||Basic video pattern generator which can support SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. You can select static video with colorbar pattern or pathological pattern from this pattern generator.|
|Pattern Gen Control PIO||Provides a memory-mapped interface for controlling the video pattern generator.|
|JTAG to Avalon Master Bridge||Provides System Console host access to the Parallel I/O (PIO) IP in the design via the JTAG interface.|
|Reference and System PLL Clocks||
This IP connects the System PLL output clock as well as the TX PLL and RX CDR reference clock to the F-tile PMA/FEC Direct PHY IP.
System PLL clock output is always set to run at a higher clock frequency than the native PMA recovered clock.
|F-tile Dynamic Reconfiguration Suite IP (DR IP)||
This module serves as an arbiter to interface between F-tile Dynamic Reconfiguration Suite IP (DR IP) and multiple SDI DR-F management controllers from different channels. The module prevents multiple controllers to request for reconfiguration simultaneously to DR IP by arbitrating the request in a round robin manner.
This module contains Reset Release Intel FPGA IP to provide a known initialized state for system logic to begin operation. The module also includes a reset delay block to further delay the signal status from the IP for a safer operation.For more information, refer to Intel Agilex Reset Release Intel FPGA IP in Intel Agilex Configuration User Guide.
Did you find the information on this page useful?