F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023

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Document Table of Contents

5.1.1. F-Tile JESD204C TX Reset Sequence

Figure 8.  F-Tile JESD204C TX Reset Sequence

The descriptions below correspond to the Figure 8:

  1. The user logic asserts the F-Tile JESD204C IP and configuration reset to the F-Tile JESD204C IP TX, j204c_tx_avs_rst_n = 0, j204c_tx_rst_n = 0, and reconfig_xcvr_reset = 1.
    Note: If you assert j204c_tx_avs_rst_n and reconfig_xcvr_reset, j204c_tx_rst_n is required to be asserted as well. You can opt to assert j204c_tx_rst_n without asserting j204c_tx_avs_rst_n and reconfig_xcvr_reset.
  2. The user logic deassert j204c_tx_avs_rst_n and reconfig_xcvr_reset and perform configurations of the PHY and IP. At the same, wait for IOPLL to lock.
  3. After all relevant PHY channels are fully in reset, the IP core asserts j204c_tx_rst_ack_n to the user logic. Knowing the relevant channels are in proper reset states, the user logic can release the reset to the IP core when possible (j204c_tx_rst_n = 1). Use j204c_tx_rst_ack_n as an indicator to deassert j204c_tx_rst_n = 1.
  4. The user logic deasserts the IP reset (j204c_tx_rst_n = 1).
  5. The IP asserts j204c_tx_avst_ready = 1. The F-Tile JESD204C TX IP core is operational.
  6. At any time when you require a reset to the MAC and PHY, you must wait for j204c_tx_rst_ack_n = 1. Assertion of j204c_tx_rst_n = 0 resets the MAC and PHY in the IP core.
  7. The IP core asserts j204c_tx_rst_ack_n = 0 to indicate that reset sequence is complete.