F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023

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5.5.2. Interrupt Top Half ISR Handler

The top half ISR handler reads the error status (F-Tile JESD204C TX and RX error status at offset 0x60) and stores the error bits meant for bottom half handling.

The ISR writes a 1 to the corresponding error bits to clear the status. The F-Tile JESD204C IP deasserts the interrupt. Then, the ISR checks the pending interrupt to ensure that the IP deasserts the interrupt.

Note: The ISR should not write all ones to the register to clear because this may clear incoming errors for different error types.

If the interrupt is not cleared, then the ISR checks the status, and stores the new error types, and OR it with the previous error status. Then, once again the ISR repeats the clearing operation and checks for pending interrupts.

Note: The error types are not grouped as correctable errors, uncorrectable errors (non fatal), and uncorrectable errors (fatal). Intel recommends that you (system designer) identify the error types and bucket them for software error handling routines.