1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5.3. Link Reinitialization
The F-Tile JESD204C IP implements a simple synchronous clear to all data and control logics during link reinitialization.
Link reinitialization occurs in two ways:
- You manually trigger link reinitialization by setting the link_reinit bit. The hardware clears the link_reinit and reinit_in_prog bits when link reinitialization completes.
- The hardware automatically triggers link reinitialization because of errors. You have full control, through the tx_err and rx_err registers, to set the specific type of errors to trigger link reinitialization automatically. The hardware clears the reinit_in_prog bit when link reinitialization completes.
Note: Link reinitialization does not initiate SYSREF re-detection. Use the sysref_singledet bit to re-detect SYSREF edge. Link reinitialization affects only the transport layer and link layer; the CSR, transceiver, and the PHY-related logics are not affected.
Did you find the information on this page useful?