F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023

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2.3. F-Tile JESD204C Intel® FPGA IP Features

The F-Tile JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP). The F-Tile JESD204C Intel® FPGA IP is the latest IP from Intel that supports the F-Tile JESD204C protocol. This IP is not backwards compatible and does not support JESD204B protocol. You can use the existing the JESD204B Intel® FPGA IP to support JESD204B protocol.

Table 7.  Brief Information about the F-Tile JESD204C Intel® FPGA IP



Protocol Features

  • Joint Electron Device Engineering Council (JEDEC) F-Tile JESD204C standard 2017
  • Device subclass:
    • Subclass 0—No deterministic latency
    • Subclass 1—Uses SYSREF signal to support deterministic latency

Core Features

  • Data rate of up to 32 Gbps for Intel® Agilex™ 7 (F-tile) devices
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E = 1 to 32
  • Supports F = 1 to 256 octets per frame
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • Interrupts and error handling support
  • System PLL clocking
  • 64/66 encoding
  • Scrambling/descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for control and status registers (CSR)
  • Dynamic generation of simulation testbench
  • Bonded and non-bonded TX PMA mode
  • Optional support for ECC M20K DCFIFO
  • Support for Transceiver Toolkit for PMA using embedded Native PHY Debug Master Endpoint (NPDME)
  • Options for sync header configurations
    • CRC-12
    • Standalone command channels
Limitations No FEC support

Typical Application

  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment

Device Family Support

  • Intel® Agilex™ 7 (F-tile) FPGA devices

Design Tools

  • Platform Designer parameter editor in the Intel® Quartus® Prime Pro Edition software for design creation and compilation
  • Timing Analyzer in the Intel® Quartus® Prime software for timing analysis

  • QuestaSim* , ModelSim* - Intel® FPGA Starter Edition, and VCS* / VCS* MX simulator software for design simulation or synthesis