F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023

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5.2. Configuration Phase

Before the hardware reset deasserts, if you want to make any changes to your F-Tile JESD204C IP configuration, you have to make the changes during the configuration phase.

The configuration phase is the only right phase to change the configuration because all configuration registers are quasi-static in nature and stable before the IP comes out of reset. The known exception to this rule is the SYSREF control registers.

If you want to make a change in the link configuration, such as disable interrupts, during mid-operation, you must always do a link re-initialization.