1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5.2. Configuration Phase
Before the hardware reset deasserts, if you want to make any changes to your F-Tile JESD204C IP configuration, you have to make the changes during the configuration phase.
The configuration phase is the only right phase to change the configuration because all configuration registers are quasi-static in nature and stable before the IP comes out of reset. The known exception to this rule is the SYSREF control registers.
If you want to make a change in the link configuration, such as disable interrupts, during mid-operation, you must always do a link re-initialization.
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