1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
Both the scrambler and descrambler are designed in a 64-bit parallel implementation and the scrambling/descrambling order starts from the first octet with MSB first.
Figure 5. Scrambling/Descrambling Order
The F-Tile JESD204C TX and RX IP core support scrambling by implementing a 64-bit parallel scrambler in each lane. The scrambler and descrambler are located in the F-Tile JESD204C IP MAC interfacing to the Avalon® streaming interface. You can enable or disable scrambling through CSR configuration for all lanes. Mixed mode operation, where scrambling is enabled for some lanes, is not permitted.
The scrambling polynomial is:
x58 + x39 + 1
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