F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023
Document Table of Contents

3.4. Scrambler/Descrambler

Both the scrambler and descrambler are designed in a 64-bit parallel implementation and the scrambling/descrambling order starts from the first octet with MSB first.
Figure 5. Scrambling/Descrambling Order

The F-Tile JESD204C TX and RX IP core support scrambling by implementing a 64-bit parallel scrambler in each lane. The scrambler and descrambler are located in the F-Tile JESD204C IP MAC interfacing to the Avalon® streaming interface. You can enable or disable scrambling through CSR configuration for all lanes. Mixed mode operation, where scrambling is enabled for some lanes, is not permitted.

The scrambling polynomial is:

x58 + x39 + 1

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