F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023
Document Table of Contents

5.8. Transceiver Toolkit

The F-Tile JESD204C Intel® FPGA IP supports the transceiver toolkit to access the PMA channels of the IP to perform tuning, eye capture, BER tests, and others.

The Intel® Quartus® Prime transceiver toolkit accesses the PMA through the PMA Avalon® memory-mapped interface.

You have the option to turn on Enable debug endpoint for PMA Avalon memory-mapped interface to enable the NPDME in the parameter editor of the F-Tile JESD204C Intel® FPGA IP. When you turn on this option, the IP instantiates an NPDME module internally. This option is available only when the PMA Avalon® memory-mapped interface is enabled.

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