F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 2/10/2023

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4.4. F-Tile JESD204C IP Component Files

The following table describes the generated files and other files that may be in your project directory. The names and types of generated files specified may vary depending on whether you create your design with VHDL or Verilog HDL.

Table 14.  Generated Files



<variation name>.v or .vhd

IP core variation file, which defines a VHDL or Verilog HDL description of the custom IP. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Intel® Quartus® Prime software.

<variation name>.cmp

A VHDL component declaration file for the IP variation. Add the contents of this file to any VHDL architecture that instantiates the IP.

<variation name>.sdc

Contains timing constraints for your IP variation.

<variation name>.qip or .ip

Contains Intel® Quartus® Prime project information for your IP variation.

<variation name>.tcl

Tcl script file to run in Intel® Quartus® Prime software.

<variation name>.sip

Contains IP library mapping information required by the Intel® Quartus® Prime software. The Intel® Quartus® Prime software generates a . sip file during generation of some Intel® FPGA IP cores. You must add any generated .sip file to your project for use by NativeLink simulation and the Intel® Quartus® Prime Archiver.

<variation name>.spd

Contains a list of required simulation files for your IP.