1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
The F-Tile JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.
TX/RX device clock
|PLL selection||The device clock is the PLL reference clock to the transceiver PLL.|
TX/RX link clock
|Line rate/66||The timing reference for the F-Tile JESD204C IP. The link clock is line rate divided by 66 because the link clock operates in a 66-bit data bus domain architecture after 64B/66B encoding.|
TX/RX frame clock
|(Link clock frequency*FCLK_MULP) MHz||The frame clock as per the JESD204C specification. The frame clock is always 1x or 2x of the link clock.|
TX/RX Avalon® memory-mapped clock
|—||The configuration clock for the F-Tile JESD204C IP control and status registers through the Avalon® memory-mapped interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75 to 125 MHz.|
TX PHY clock
The PHY clock internally generated from the transceiver parallel clock for the TX path.
|Transceiver reconfiguration clock
|—||The transceiver reconfiguration clock. The frequency range of this clock is 100 MHz.|
|System PLL clock
|System PLL clock frequency >= Native clock frequency||The F-Tile system PLL clock frequency is user-defined. The system PLL clock frequency is greater or equal to the native clock frequency.|
Frame Clock and Link Clock
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