AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

ID 683875
Date 1/28/2022

1. Tutorial Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.3
This document demonstrates how to debug an Intel® Stratix® 10 Partial Reconfiguration design with the Signal Tap Logic Analyzer.

Partial Reconfiguration is an advanced design flow that allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can define multiple personas to occupy the same design region, without impacting operation in other regions.

This application note extends the Partial Reconfiguration (PR) process described in AN 825: Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board to the Signal Tap logic analyzer debugging environment.

The Signal Tap logic analyzer, available in the Intel® Quartus® Prime software, captures and displays the real-time signal behavior in an Intel FPGA design. Use the Signal Tap logic analyzer to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.

The Signal Tap logic analyzer supports data acquisition in the static and PR regions. Moreover, you can debug multiple personas present in a PR region and multiple PR regions.

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