AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

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ID 683875
Date 1/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Tutorial Overview 2. Tutorial Walkthrough 3. Tutorial Results 4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design
1. Tutorial Overview x
1.1. PR Debug Considerations 1.2. Tutorial Software and Hardware Requirements 1.3. Tutorial Design Description 1.4. Downloading the Tutorial Design
1.4. Downloading the Tutorial Design x
1.4.1. Tutorial Design Files
2. Tutorial Walkthrough x
2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision x
2.2.1. Preparing the Static Region 2.2.2. Preparing the Default PR Persona
2.4. Step 4: Configuring Signal Tap Logic Analyzer x
2.4.1. Tapping Signals in the Implementation Persona 2.4.2. Configuring Data Acquisition 2.4.3. Setting Trigger Conditions
2.4.2. Configuring Data Acquisition x
2.4.2.1. Add Acquisition Clock 2.4.2.2. Add Storage Parameters
3. Tutorial Results x
3.1. Waveforms for Slow Implementation 3.2. Waveforms for Default Implementation 3.3. Waveforms for Empty Implementation
1. Tutorial Overview
2. Tutorial Walkthrough
3. Tutorial Results
4. Document Revision History for AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

2.7. Step 7: Performing Data Acquisition

After loading the appropriate .rbf onto the board, start data acquisition on the Signal Tap logic analyzer.

To perform data acquisition:

  1. Make sure that the Signal Tap Logic Analyzer loads the .stp file in the current active revision.
  2. In the top right corner of the Signal Tap window, set up the JTAG connection to the board with the following options:
    Option Description
    Hardware USB-BlasterII
    Device 1SG280L
    Bridge Index 0

    Bridge index is set to 0 for tapping signals in the PR region.

    Figure 26. JTAG Configuration
  3. On the Signal Tap toolbar, click Run Analysis .
    The analysis may take a few minutes.
    When the analysis finishes, the Signal Tap Logic Analyzer loads the waveforms to the window.
The following section displays the resultant waveforms for all PR configurations.
Level Two Title