AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

ID 683875
Date 1/28/2022
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2.5. Step 5: Generating Programming Files

The design is now ready for compilation. The Intel® Quartus® Prime Compiler generates files that you then program into the FPGA. This Partial Reconfiguration design requires generating .sof and .rbf files.

Compile each revision (blinking_led, blinking_led_slow, blinking_led_default, and blinking_led_empty) in the project as follows:

  1. Change the current revision by clicking Project > Revisions and selecting a revision to set as the current revision.
  2. Click Processing > Start Compilation.
  3. Repeat these steps for each revision.
Alternatively, you can compile the revisions with the following commands:
quartus_sh --flow compile blinking_led -c blinking_led
quartus_sh --flow compile blinking_led -c blinking_led_slow
quartus_sh --flow compile blinking_led -c blinking_led_default
quartus_sh --flow compile blinking_led -c blinking_led_empty

If the compilation succeeds, the output files are now in the output_files directory.