1.1. PR Debug Considerations
Debugging a PR design requires planning. Before compiling, you must decide whether to tap signals in the static region, which PR region you want to debug, and which personas in the PR region you want to debug.
If you have multiple personas in your design, you must also instantiate the Intel® Configuration Reset Release Endpoint to Debug Logic IP in each PR region. This IP ensures proper function by providing a reset signal to debug logic, such as Signal Tap, after partial reconfiguration. This reset signal must be high during configuration, and then this reset signal must go low once partial reconfiguration is complete. You must not release this reset signal after releasing the PR logic reset. The time of this reset release affects the Signal Tap power-up trigger feature. The reset signal must stay low until the next reconfiguration.
Error(11176): Alt_sld_fab_1.alt_sld_fab_1.alt_sld_fab_1: The Intel Configuration Reset Release
Endpoint to Debug Logic IP must be instantiated to provide the reset signal to the debug logic,
such as Signal Tap, etc. after the partial configuration is performed.
To ensure visibility, the debugging fabric must extend to all the regions that you want to tap. The Intel® Quartus® Prime software enables you to extend the debug fabric by using debug bridge components: the SLD JTAG Bridge Agent Intel® FPGA IP and the SLD JTAG Bridge Host Intel® FPGA IP.
To incorporate these components to the design, for each PR region in the design that you want to debug:
- Instantiate the SLD JTAG Bridge Agent Intel FPGA IP in the static region.
- Instantiate the SLD JTAG Bridge Host Intel FPGA IP and the Intel Configuration Reset Release Endpoint to Debug Logic in the PR region of the default persona.
- Instantiate the SLD JTAG Bridge Host Intel FPGA IP and the Intel Configuration Reset Release Endpoint to Debug Logic on the implementation revisions that you want to debug.
SLD JTAG Bridge Index
The index is an attribute of the SLD JTAG Bridge Agent that uniquely identifies bridge agents present in the design. You can find information regarding the bridge index in the synthesis report (<base revision>.syn.rpt), by looking under JTAG Bridge Agent Instance Information. The bridge index for the root partition is always None.