AN 841: Signal Tap Tutorial for Intel® Stratix® 10 Partial Reconfiguration Design

ID 683875
Date 1/28/2022
Public
Give Feedback

2.2.2. Preparing the Default PR Persona

In this phase you instantiate the SLD JTAG Bridge Host Intel® FPGA IP and the Intel Configuration Reset Release Endpoint to Debug Logic IP in the PR region that you want to debug.
  1. Add the SLD JTAG Bridge Host Intel® FPGA IP to the design:
    1. In the IP Catalog (Tools > IP Catalog), type SLD JTAG Bridge Host, and double-click the SLD JTAG Bridge Host Intel® FPGA IP .
    2. In the New IP Variant dialog box, type sld_host as the file name, and then click Create.
      Figure 10. New IP Variant Dialog Box
    3. In the parameter editor, keep the default parameterization for sld_host. Click Generate HDL and then click Generate.

      Save your changes, if prompted.

      Figure 11. SLD JTAG Bridge Host Intel® FPGA IP Parameters
      The parameter editor generates the sld_host.ip IP variation file and adds the file to the blinking_led project.
    4. Close the parameter editor.
    5. Verify whether the sld_host IP variant appears in the IP Components tab of the Project Navigator.
      Figure 12. sld_host IP Variant in Project Navigator
      If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the sld_host.ip file, and add it to the project.
    6. In the blinking_led.sv file, instantiate the sld_host IP in the default persona by uncommenting the following block of code:
      //==================
      //Uncomment this block to enable Signal Tap
      
      sld_host u_sld_hostled_two_on (
       .tck  (tck),  //  input,  width = 1, connect_to_bridge_host.tck
       .tms  (tms),  //  input,  width = 1, .tms
       .tdi  (tdi),  //  input,  width = 1, .tdi
       .vir_tdi (vir_tdi), //  input,  width = 1, .vir_tdi
       .ena  (ena),  //  input,  width = 1, .ena
       .tdo  (tdo)   //  output, width = 1, .tdo
      );
      
      //==================
  2. Add the Intel Configuration Reset Release Endpoint to Debug Logic IP to the design:
    1. In the IP Catalog (Tools > IP Catalog), type Configuration Reset Release Endpoint, and double-click the Intel Configuration Reset Release Endpoint to Debug Logic.
    2. In the New IP Variant dialog box, type config_reset_release_endpoint as the file name, and then click Create.
      Figure 13. New IP Variant Dialog Box
    3. In the parameter editor, keep the default parameterization for config_reset_release_endpoint. Click Generate HDL and then click Generate.

      Save your changes, if prompted.

      Figure 14. Intel Configuration Reset Release Endpoint to Debug Logic Parameters
      The parameter editor generates the config_reset_release_endpoint.ip IP variation file and adds the file to the blinking_led project.
    4. Close the parameter editor.
    5. Verify whether the config_reset_release_endpoint IP variant appears in the IP Components tab of the Project Navigator.
      Figure 15. config_reset_release_endpoint IP Variant in Project Navigator
      If the IP variant does not appear in the Project Navigator, click Project > Add/Remove Files in Project, find the config_reset_release_endpoint.ip file, and add it to the project.
    6. In the blinking_led.sv file, instantiate the config_reset_release_endpoint IP in the default persona by uncommenting the following block of code:
      //==================
      //Uncomment this block to enable Signal Tap
      
      config_reset_release_endpoint u_config_reset_release_endpoint (.conf_reset (reset)  //   input,  width = 1, conf_reset_in.reset
      );
      
      //==================
  3. In the blinking_led.sv file, update the port definition of the default PR persona to include the following ports by uncommenting the following block of code:
    //===================
    // Uncomment this block to enable Signal Tap
    
    input wire reset,
    input wire tck,
    input wire tms,
    input wire tdi,
    input wire vir_tdi,
    input wire ena,
    output wire tdo,
    
    //===================
  4. In the top.sv file, update the instantiation of the persona to include the sld_host and config_reset_release_endpoint ports by uncommenting the following block of code:
    //===================
    //Uncomment this block to enable Signal Tap
    
    .reset   (connect_to_conf_rst),
    .tck	(tck),      //   input,  width = 1, connect_to_bridge_host.tck
    .tms	(tms),      //   input,  width = 1,                       .tms
    .tdi	(tdi),      //   input,  width = 1,                       .tdi
    .vir_tdi (vir_tdi),  //   input,  width = 1,                       .vir_tdi
    .ena	(ena),      //   input,  width = 1,                       .ena
    .tdo	(tdo),      //  output,  width = 1,                       .tdo
    
    //====================