AN 825: Partially Reconfiguring a Design: on Intel® Stratix® 10 GX FPGA Development Board

ID 683880
Date 12/07/2020

Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 20.3
This application note demonstrates transforming a simple design into a partially reconfigurable design, and implementing the design on the Intel® Stratix® 10 GX FPGA development board.

The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the Intel® Quartus® Prime Pro Edition software introduces a new and simplified compilation flow for partial reconfiguration.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space
Note: This tutorial uses the Intel® Stratix® 10 GX FPGA development board on the bench, outside of the PCIe* slot in your workstation.