AN 825: Partially Reconfiguring a Design: on Intel® Stratix® 10 GX FPGA Development Board

ID 683880
Date 12/07/2020
Public

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source and connects the output to four LEDs on the board. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning