AN 825: Partially Reconfiguring a Design: on Intel® Stratix® 10 GX FPGA Development Board

Download PDF
ID 683880
Date 12/07/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 825: Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board

Reference Design Walkthrough

The following steps describe the application of partial reconfiguration to a flat design. The tutorial uses the Intel® Quartus® Prime Pro Edition software for the Intel® Stratix® 10 GX FPGA development board:
Note: Unlike AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board, this tutorial does not require the addition of a Partial Reconfiguration Controller IP core. This difference is because Intel® Stratix® 10 devices support PR over JTAG using the hard JTAG pins of the FPGA.
Related Information
Level Two Title