F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

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ID 683872
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices 3.14.1.3. Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning 5.9. Compiling a F-Tile Design with VHDL Configuration File as the Top Level Module
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool 6.5. F-Tile FHT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation A.4. Transceiver Toolkit Helper Script A.5. F-Tile Tuning Guidelines
A.4. Transceiver Toolkit Helper Script x
A.4.1. Introduction A.4.2. Executing the Script
A.5. F-Tile Tuning Guidelines x
A.5.1. Introduction A.5.2. Equalization Techniques Overview A.5.3. Equalization Recommendations for F-Tile FGT PMA Transceivers A.5.4. F-Tile FGT PMA Tuning Guide A.5.5. Equalization Recommendations for F-Tile FHT PMA Transceivers A.5.6. F-Tile FHT PMA Tuning Guide A.5.7. Appendix
A.5.1. Introduction x
A.5.1.1. F-Tile PMA Overview A.5.1.2. Equalization Techniques Overview
A.5.1.2. Equalization Techniques Overview x
A.5.1.2.1. FGT Transmitter Equalization Tuning Taps A.5.1.2.2. FGT Receiver Adaptation A.5.1.2.3. FGT Media Selection A.5.1.2.4. FHT Transmitter Equalization Tuning Taps
A.5.3. Equalization Recommendations for F-Tile FGT PMA Transceivers x
A.5.3.1. F-Tile FGT Transmitter Equalization Parameters A.5.3.2. F-Tile FGT Transmitter Setting Recommendations A.5.3.3. F-Tile FGT Receiver Equalization Parameters A.5.3.4. F-Tile FGT Receiver Setting Recommendations
A.5.4. F-Tile FGT PMA Tuning Guide x
A.5.4.1. F-Tile FGT NRZ Tuning Flow A.5.4.2. F-Tile FGT Hardware Setup A.5.4.3. F-Tile FGT Tuning Examples
A.5.4.3. F-Tile FGT Tuning Examples x
A.5.4.3.1. Example 1 : F-Tile FGT 25 Gbps NRZ Design A.5.4.3.2. Example 2 : F-Tile FGT 58 Gbps PAM4 and FEC Design A.5.4.3.3. Example 3 : F-Tile FGT 5 Gbps NRZ Design
A.5.5. Equalization Recommendations for F-Tile FHT PMA Transceivers x
A.5.5.1. F-Tile FHT Transmitter Equalization Parameters A.5.5.2. F-Tile FHT Transmitter Setting Recommendations A.5.5.3. F-Tile FHT Receiver Equalization Parameters
A.5.6. F-Tile FHT PMA Tuning Guide x
A.5.6.1. F-Tile FHT Tuning Flow A.5.6.2. F-Tile FHT Hardware Setup A.5.6.3. F-Tile FHT Tuning Examples
A.5.6.3. F-Tile FHT Tuning Examples x
A.5.6.3.1. Example 1 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.5.6.3.2. Example 2 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.5.6.3.3. Example 3 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.5.6.3.4. Example 4 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.5.6.3.5. Example 5 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.5.6.3.6. Example 6 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.5.6.3.7. Example 7 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.5.6.3.8. Example 8 : F-Tile FHT 25 Gbps NRZ Design (Long Reach) A.5.6.3.9. Example 9 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.5.6.3.10. Example 10 : F-Tile FHT 50 Gbps PAM4 Design (Long Reach)
A.5.7. Appendix x
A.5.7.1. FCI Backplane Design A.5.7.2. F-Tile FGT Tuning Script A.5.7.3. F-Tile FGT Attribute Access Sequence
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

A.4.2. Executing the Script

The design used to execute and test the script is an FGT FEC direct 400G 8 channels PAM4 design.

In the Tcl console window type: source ttk_helper_ftile.tcl
The Messages window of the Tcl console displays several pages of information about the script as shown below.
Figure 160. Script Source Output in Messages Window
There is information in the Messages window for each function with an example to guide you on how to pass acceptable parameters for the function calls. All 56 functions are shown below: 
rd_channel_ftile {phy channel address verbose}
to read and printout use e.g. rd_channel_file ftile_phy_0 3 0x47830 1
when only reading without printing use e.g. set d [rd_channel_ftile ftile_phy_0 3 0x47830 0]

rd_channel_pdp {phy channel offset verbose}
to read and printout use e.g. rd_channel_pdp ftile_phy_pdp_0 0 0x60C0 1
when only reading without printing use e.g. set d [rd_channel_pdp ftile_phy_pdp_0 0 0x60C0 1]

wr_channel {phy channel offset newval verbose}
example usage wr_channel ftile_phy_0 1 0x207 0x91 1

rmw_channel {phy channel offset mask newval verbose}
example usage rmw_channel ftile_phy_0 0 0x47830 0x0000FC00 [expr 35 << 10] 1

rmw_channel_ftile {phy channel address mask newval verbose}
example usage (set maintap to 35) rmw_channel_ftile ftile_phy_0 1 0x47830 0x0000FC00 [expr 35 << 10] 1

wr_channel_ftile {phy channel address newval verbose}

wr_channel_pdp {phy channel offset newval verbose}
example usage wr_channel ftile_phy_pdp_0 0 0x1E0 0x00000001 1

rmw_channel_pdp {phy channel offset mask newval verbose}
example usage rmw_channel_pdp ftile_phy_pdp_0 0 0x1E0 0x00000001 0x00000001 1

reset_phy {phy verbose}
example usage reset phy using soft CSR : reset_phy ftile_phy_0 1
Note that this function does not check whether soft CSR is enabled or not when Phy-Direct IP is used

reset_assert_phy {phy verbose}
example usage reset assert phy using soft CSR : reset_assert_phy ftile_phy_0 1
Note that this function does not check whether soft CSR is enabled or not when Phy-Direct IP is used

reset_deassert_phy {phy verbose}
example usage reset deassert phy using soft CSR : reset_deassert_phy ftile_phy_0 1
Note that this function does not check whether soft CSR is enabled or not when Phy-Direct IP is used

cpi_request_fgt {phy channel data opcode assert set_getn verbose

get_cpidata {phy channel data opcode verbose}

get_fom {phy channel verbose}
example usage (read from from channel 7):  get_fom ftile_phy_0 7 0

get_vga {phy channel verbose}  
example usage (read from from channel 7):  get_vga ftile_phy_0 7 0

get_ctle {phy channel verbose}  
example usage (read from from channel 7):  get_ctle ftile_phy_0 7 0

set_media_mode {phy number_of_lanes media_mode verbose}  
example usage to set to VSR Low Loss (8dB)   :  set_media_mode ftile_phy_0 8 0x14 0
example usage to set to VSR High Loss (10dB) :  set_media_mode ftile_phy_0 8 0x15 0
example usage to set to FW Default           :  set_media_mode ftile_phy_0 8 0x10 0
Note that VSR High Loss mode is not supported on Rev A0 silicon

get_firmware_fgt {phy verbose}
example to get firmware version for fgt:  get_firmware_fgt ftile_phy_0 1

get_firmware_fht {phy verbose}
example to get firmware version for fht :  get_firmware_fht ftile_phy_0 1

get_silicon_rev {phy verbose}
example to get silicon revision :  get_silicon_rev ftile_phy_0 0

readout_adaptation_mode_fgt {phy channel verbose}
example to get adapation mode for fgt for channel 1:  readout_adaptation_mode_fgt ftile_phy_0 1 0

read_recclk_status {phy channel verbose}  
example usage to read the status of the recovered clock output :  read_recclk_status ftile_phy_0 0 0

enable_recclk {phy channel verbose}
example usage to enable the recovered clock from phy_15  :  enable_recclk ftile_phy_0 0 0

disable_recclk {phy channel verbose}
example usage to disable the recovered clock output on phy_15  :  disable_recclk ftile_phy_0 0 0

get_rx_ready_fgt {phy channel verbose}  
example usage :  get_rx_ready_fgt ftile_phy_0 0 0

get_rx_ready_fht {phy channel verbose}  
example usage :  get_rx_ready_fht ftile_phy_0 0 0

get_tx_ready_fgt {phy channel verbose}  
example usage :  get_tx_ready_fgt ftile_phy_0 0 0

compare_xcvr_channels {phy ch1 ch2 start_addr stop_addr}
example usage compare_xcvr_channels ftile_phy_0 0 1 0x0 0xF

set_serial_loopback {phy number_of_lanes serial_loop verbose}
the corresponding reconfig_pdp or phy_pdp (AVMM1) will be used using the same index number as the phy
example to turn serial loopback ON for all 8 channels of ftile_phy_0  :  set_serial_loopback ftile_phy_0 8 1 1

set_rev_par_loopback {phy number_of_lanes rev_parallel verbose}
this information can be obtained by looking that the claimed phy's and pdp_phy's
"Note : if Phy Direct IP with FEC enabled is used enabling/disabling PMA reverse parallel loopback will not work with system console"
"Note : as it requires user logic to start the generation of the tx_am_gen_start pulses to reach tx_ready after tx_reset"
example to turn the PMA reverse parallel loopback ON for all channels of ftile_phy_0 :  set_rev_par_loopback ftile_phy_0 8 1 1

set_par_loopback {phy number_of_lanes parallel verbose}
this information can be obtained by looking that the claimed phy's and pdp_phy's
"Note : if a Phy Direct IP with FEC enabled is used then turning off the parallel loopback requires a full reset of the phy (to be done outside of system console)"
example to turn the parallel loopback ON for all channels of ftile_phy_0 :  set_par_loopback ftile_phy_0 8 1 1

set_tx_invert_polarity {phy channel tx_polarity verbose}
example to invert the tx_polarity on channel 2 on ftile_phy_0 :  set_tx_invert_polarity ftile_phy_0 2 1 1

set_rx_invert_polarity {phy channel rx_polarity verbose}
example to invert the rx_polarity on channel 2 on ftile_phy_0 :  set_rx_invert_polarity ftile_phy_0 2 1 1

run_prbs_test {remote_phy remote_ch dut_phy dut_ch prbs_pattern runtime_ms error_count verbose}
example to run a BER Test using PRBS31 for 1 second from phy 0 channel 0 to phy 3 channel 0
and injecting 10 errors :  run_prbs_test ftile_phy_0 0 ftile_phy_3 0 $PRBS31 1000 10 0

start_prbs_tx {phy channel prbs_pattern verbose}
example to start BER Test using PRBS31 pattern on tx of channel 0 on ftile_phy_0 :  start_prbs_tx ftile_phy_0 0 $PRBS31 0

start_prbs_rx {phy channel prbs_pattern verbose}
example to start BER Test using PRBS31 pattern on rx of channel 0 on ftile_phy_0 :  start_prbs_rx ftile_phy_0 0 $PRBS31 0

inj_prbs_err_fht {phy channel verbose}

prbs_err_cnt_ctrl_fht {phy channel start stop clear}

prbs_err_cnt_fht {phy channel}

prbs_tx_cnt_fht {phy channel}

prbs_ber_fht {phy channel}

prbs_test_fht {phy channel prbs_pattern verbose}
example: prbs_test_fht ftile_phy_0 0 4 0
prbs_pattern: 7/9/11/23/31 --> 0/1/2/3/4

rsfec_test {phy_pdp eth_rate num_of_lane test_time_sec num_of_test file_id}
example: rsfec_test ftile_phy_pdp_0 200 4 1 10 stdout

inject_prbs_errors {phy channel error_number verbose}
example to inject 10 errors on channel 0 on ftile_phy_0 :  inject_prbs_errors ftile_phy_0 0 10 0

read_prbs_error_count {phy channel}
example to get the prbs errorcount on channel 0 on ftile_phy_0 :  set errorcount [read_prbs_error_count ftile_phy_0 0]

clear_prbs_error_count {phy channel}
example to clear the prbs errorcount on channel 0 on ftile_phy_0 : clear_prbs_error_count ftile_phy_0 0 

stop_prbs_tx {phy channel verbose}
example to stop BER Test on tx of channel 0 on ftile_phy_0 :  stop_prbs_tx ftile_phy_0 0 0

stop_prbs_rx {phy channel prbs_pattern verbose}
example to start BER Test using PRBS31 pattern on rx of channel 0 on ftile_phy_0 :  stop_prbs_rx ftile_phy_0 0 0

program_tx_pma_settings_fht {phy channel fht_tx_pretap_3 fht_tx_pretap_2 fht_tx_pretap_1 fht_tx_maintap fht_tx_posttap_1 fht_tx_posttap_2 fht_tx_posttap_3 fht_tx_posttap_4 verbose}
example to set FHT Tx EQ settings (pre_tap_1=56, main_tap=30, post_tap_1=60, post_tap_2=56 on ftile_phy_0 :  program_tx_pma_settings_fht ftile_phy_0 0 0 0 56 30 60 56 0 0 1
note that Tx EQ settings provided are similar to .qsf assignment settings (using twos_complement and multiplication)
note that no check is being done whether the values entered or valid or not, this is the responsibility of the user
to mute the transmitter just set all values to 0

show_phy_direct_info {phy_pdp}
example to show phy info ON of ftile_phy_pdp_0 :  show_phy_direct_info ftile_phy_pdp_0 1

show_pma_settings_ftile {phy number_of_lanes do_ehm}  
example usage (with ehm at 1e-6 enabled :  show_pma_settings_ftile ftile_phy_0 8 1
Note that if you use ehm it will take more time for it to complete

measure_ehm_fgt {phy channel ber_target verbose}  
example usage measure ehm on fgt with ber target of 1E-6:  measure_ehm_fgt ftile_phy_0 0 6 0

get_snr_fht {phy channel}
example usage measure snr on fht :  get_snr_fht ftile_phy_0 0

get_ehm_fht {phy channel bin_threshold test_length}   
example usage measure ehm on fht :  get_ehm_fht ftile_phy_0 0 2 10

set_txeq_settings {phy number_of_lanes maintap pretap1 pretap2 posttap1 verbose} 
example usage :  set_txeq_settings ftile_phy_0 1 35 5 0 0 0

set_rxeq_settings {phy number_of_lanes hf_boost vga_gain dfe_tap verbose} 
example usage :  set_rxeq_settings ftile_phy_0 1 30 10 0 1

Following is the list of F-Tile PHY's claimed (reconfig_xcvr/avmm2). You should use the ftile_phy_<i> as phy identifier in the functions: 

Phy : "ftile_phy_0" ---> Hierarchy Path: 
{Generate_transceiver_block[0].instx|
Generate_txrx_pcs_64b66b_fgt[0].txrx_pcs_64b66b_fgt_x|
Generate_phy_direct[0].phy_direct_inst|directphy_f_0|
dphy_sip_inst|f_dphy_adme[0].f_dphy_adme_inst|f_dphy_adme|avmm2} Slave: 0x1800000
Phy : "ftile_phy_1" ---> Hierarchy Path: 
{Generate_transceiver_block[1].instx|
Generate_txrx_pcs_64b66b_fgt[0].txrx_pcs_64b66b_fgt_x|
Generate_phy_direct[0].phy_direct_inst|directphy_f_0|
dphy_sip_inst|f_dphy_adme[0].f_dphy_adme_inst|f_dphy_adme|avmm2} Slave: 0x2000000

Following is the list of F-Tile PDP PHY's claimed (reconfig_xcvr/avmm1). You should use the ftile_phy_<i> as phy identifier in the functions: 

Phy_pdp : "ftile_phy_pdp_0" ---> Hierarchy Path: 
{Generate_transceiver_block[0].instx|
Generate_txrx_pcs_64b66b_fgt[0].txrx_pcs_64b66b_fgt_x|
Generate_phy_direct[0].phy_direct_inst|directphy_f_0|dphy_sip_inst|
f_dphy_adme[0].f_dphy_adme_inst|f_dphy_adme|avmm1} Slave: 0x800000
Phy_pdp : "ftile_phy_pdp_1" ---> Hierarchy Path: 
{Generate_transceiver_block[1].instx|
Generate_txrx_pcs_64b66b_fgt[0].txrx_pcs_64b66b_fgt_x|
Generate_phy_direct[0].phy_direct_inst|directphy_f_0|
dphy_sip_inst|f_dphy_adme[0].f_dphy_adme_inst|f_dphy_adme|avmm1} Slave: 0x1000000

You can view the complete print out in the Messages window that displays each function with an example to guide you what parameter to pass for the acceptable function calls.

For example, you can use show_pma_setting_ftile function to get the pma_settings of specific channels of a PMA Direct IP or an F-Tile Hard IP or a Multirate IP. From the output hint in the Messages window, you can see how to make the function call. 

show_pma_settings_ftile {phy number_of_lanes do_ehm} 
example usage (with ehm at 1e-6 enabled :  show_pma_settings_ftile ftile_phy_0 8 1}
{Note that if you use ehm it will take more time for it to complete}

In the example, if you want to view the PMA settings for phy_0, 8 channels, with eye height measurement (do_ehm=1). You should enter the following function call in the Tcl console window: 

show_pma_settings_ftile ftile_phy_0 8 1
If you want to see the PMA settings for phy_0, 8 channels, without eye height measurement, you can enter the following function call in the Tcl console window: 
show_pma_setting_ftile ftile_phy_0 8 0
When you run the function the following output is displayed in the Tcl console:
Figure 161. Show PMA Setting Function Call Output

You can view a lot of useful information to help you understand your channel such as PMA type, Quad and channel used, line encoding type, loopback type, TX and RX equalization taps values, adaptation mode as well as useful information to help you examine the channel health such as tx and rx ready status, FOM value (larger the better). The eye height measurement function is currently available for the auto adaptation mode only.

You can see that the top, middle and bottom eye height values are printed out. By adjusting the TX and RX equalization parameter values, you can see changes in the eye height values. Hence, you can find the optimal equalization parameter values to generate the largest eye opening.

For testing, if you want to enable serial internal loopback for 8 channels, based on the script output hint you can use the following function call: 
set_serial_loopback {phy number_of_lanes serial_loop verbose}
the corresponding reconfig_pdp or phy_pdp (AVMM1) will be used using the same index number as the phy
example to turn serial loopback ON for all 8 channels of ftile_phy_0  :  set_serial_loopback ftile_phy_0 8 1 1
if you use the following incorrect function call: 
set_serial_loopback ftile_phy_0 4 1 0
Figure 162. Serial Loopback Function Call Failed Output

The script output hint shows that this is an illegal function call and displays the following message:

number_of_lanes: 4 provided does not match with the amount of lanes in the phy: 8: operation aborted
You must modify the function call as follows to make it legal: 
set_serial_loopback ftile_phy_0 8 1 1
You can now see that serial loopback is enabled for all the channels. You can also modify the script to achieve the individual channel’s loopback control. The following figure displays the information for the 8 channel serial loopback enabled.
Figure 163. Show PMA Setting Function Call Output with 8 Channels Loopback Enabled
To run a BER test, you can use the run_prbs_test function to send the PRBS31 pattern for 1 second (1000) and inject 10 errors. You can see that the error count displayed is 0xa which is 10 in decimal as expected, as shown in the following figure.
Figure 164. BER Function Call Output
The script also has an RS-FEC testing function to check FEC’s error correction capability as shown in the script print out: 
rsfec_test {phy_pdp eth_rate num_of_lane test_time_sec num_of_test file_id}
example: rsfec_test ftile_phy_pdp_0 200 4 1 10 stdout

The design used to run the test is a FGT FEC direct 400G-8 design. The example print out displays the function call for a 200G 4 channel design. You can modify the function call for a 400G 8 channel design that is used to execute this script as shown below: 

rsfec_test ftile_phy_pdp_0 400 8 1 10 stdout
The following figure displays the results of the RS-FEC test function call in the Tcl console.
Figure 165. RSFEC Test Function Call Output
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