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2.2.5. Topologies
F-Tile-supported protocols use EMIBs, PMAs, and streams for the relevant hard IP. Because hard IPs in multi-protocol F-Tile designs share PMAs and EMIBs, specific pairings of PMAs and EMIBs are required to support different combinations of hard IPs, PTP-enabled ports, and bandwidths. These pairings are called topologies. F-Tile supports 15 pre-defined topologies, each with different constraints. Every F-Tile design must follow one of these topologies. You cannot dynamically reconfigure from one topology to another. Dynamic reconfiguration is allowed only within a topology.
Select a topology based on the following design considerations:
- Do you need PCIe* ?
- Do you need IEEE 1588 precision time protocol ports?
- Do you need FHT PMA lanes?
If you need to implement multiple hard IPs, verify that there is a topology that meets your requirements.
- If your F-Tile design does not utilize all tile resources, there may be more than one topology that meets your requirements.
- If more than one topology meets your requirements, select the topology with the most PMAs and streams available to ensure that the maximum number of hard IPs can be implemented.
- Use the F-Tile Channel Placement Tool to plan your design; it shows available PMA, stream, and EMIB locations for each topology.
Topology | PCIe* Hard IP | 400G Hard IP | 200G Hard IP | |||||||
---|---|---|---|---|---|---|---|---|---|---|
Avail-ability | Config-uration | Avail-ability | Configuration | Avail-ability | Configuration 4 | |||||
PMA | PTP | Number of PMAs | Number of Streams | Number of PMAs | Number of Streams | |||||
1 | Yes | 1x PCIe* x16 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
2 | Yes | 2x PCIe* x8 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
3 | Yes | 1x PCIe* x16 | Yes | FHT | Yes | 4 | 4 | No | N/A | N/A |
4 | Yes | 4x PCIe* x4 | No | N/A | N/A | N/A | N/A | No | N/A | N/A |
5 | No | N/A | Yes | FHT | No | 4 | 16 | Yes | 8 | 8 |
6 | No | N/A | Yes | FHT | Yes | 4 | 16 | Yes | 6 | 6 |
6a | No | N/A | Yes | FGT (4) + FHT (4) | Yes | 8 | 16 | Yes | 6 | 6 |
7 | Yes | 1x PCIe* x4 | Yes | FHT | Yes | 4 | 16 | No | N/A | N/A |
8 | Yes | 1x PCIe* x8 | Yes | FHT | Yes | 4 | 10 | No | N/A | N/A |
9 | Yes | 2x PCIe* x4 | Yes | FHT | Yes | 4 | 10 | No | N/A | N/A |
10 | No | N/A | Yes | FGT | No | 8 | 16 | Yes | 8 | 8 |
11 | No | N/A | Yes | FGT | Yes | 8 | 16 | Yes | 6 | 6 |
12 | Yes | 1x PCIe* x8 | Yes | FGT | Yes | 8 | 11 | No | N/A | N/A |
13 | Yes | 2x PCIe* x4 | Yes | FGT | Yes | 8 | 11 | No | N/A | N/A |
14 | Yes | 1x PCIe* x4 | Yes | FGT | Yes | 12 | 16 | No | N/A | N/A |
15 | No | N/A | Yes | FGT | Yes | 16 | 16 | No | N/A | N/A |
17 | No | N/A | Yes | FHT | Yes | 4 | 4 | Yes | 4 | 4 |
FGT | Yes | 12 | 12 | |||||||
18 | No | N/A | Yes | FHT |
No |
4 |
4 |
Yes | 8 | 8 |
FGT |
No |
8 |
12 |
- Topology 2: 2x PCIe* x8:
- The PCIe* hard IP implements two ports of PCIe* x8.
- You cannot implement any other protocol interface in this F-Tile.
- 400G hard IP and 200G hard IP are unavailable.
-
Topology 3: 1x PCIe* x16 + 400G Hard IP (FHT) with PTP is a superset of Topology 1: 1x PCIe* x16. That means if your target implementation works with Topology 1: 1x PCIe* x16, it also works with Topology 3: 1x PCIe* x16 + 400G Hard IP (FHT) with PTP.
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Topology 6a: Mix of Topology 6 and 11. It uses the mixed transceiver mode for 400G Hard IP with four FHT PMA and four FGT PMA (Quad2). In this topology, the 200G Hard IP supports a maximum data rate of 150G with seven FGT PMAs (Quad0: 0-3 and Quad1: 0-2).
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Topology 18: Similar to Topology 10 with the additional ability to use FHT channels for addition of 100G of data bandwidth. You can only use FHT channels in 100G-4 or 100G-2 configurations. You can instantiate the FGT channels as either 25G or 50G. The FGT Quad3 and Quad2 channels can only use the E400 block. FGT Quad1 and Quad0 can only use the E200 block. All channels are not limited to Ethernet use only. You can also use ANLT on Ethernet channels. Dynamic reconfiguration is supported for the following use cases:
- Dynamic reconfiguration is supported within the same 100G fracture
- Dynamic reconfiguration is supported within the same FHT or FGT Quad
- FHT PMAs map to the top E400 100G fracture only
- FGT Quad3 maps to the second E400 100G fracture from the top
- FGT Quad2 maps to the third or fourth E400 100G fracture from the top
Table 13. Maximum Bandwidth Achieved Using Topology 18 = 600 Gbps Hard IP Channels Maximum Bandwidth Configuration Placement 400G FHT 100G 4x25G or 2x50G 50G lanes can only be placed on FHT channels 3 and 2 FGT Quad 3 100G 4x25G or 2x50G 50G lanes can only be placed on FGT Quad 3, Channels 1 and 0 FGT Quad 2 200G 4x50G No 50G channel placement restrictions 200G FGT Quad 1/0 200G 8x25G or 4x50G No channel placement restrictions
Section Content
Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example
Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example
Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example