F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

Download PDF
ID 683872
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Overview 2. F-Tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. F-Tile PMA/FEC Direct PHY Design Implementation 6. Supported Tools 7. Debugging F-Tile Transceiver Links 8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide A. Appendix
1. F-Tile Overview x
1.1. Device Family Support
2. F-Tile Architecture x
2.1. F-Tile Building Blocks 2.2. F-Tile Placement Rules 2.3. PMA Architecture 2.4. Clock Architecture
2.1. F-Tile Building Blocks x
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2. F-Tile Placement Rules x
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
2.2.1. PMA-to-Fracture Mapping x
2.2.1.1. FHT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.2. FGT-PMA-to-400G-Hard-IP-Fracture Mapping 2.2.1.3. FGT-PMA-to-200G-Hard-IP-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture x
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
2.2.5. Topologies x
2.2.5.1. Topology 5: 400G Hard IP (FHT) + 200G Hard IP (FGT) Example 2.2.5.2. Topology 6a: 400G Hard IP with Mixed Transceiver Mode Example 2.2.5.3. Topology 14: 1x PCIe x4 + 400G Hard IP (FGT) with PTP Example
2.2.8. Bonding Placement Rules x
2.2.8.1. Bonded Lanes Use Case 1 2.2.8.2. Bonded Lanes Use Case 2
2.3. PMA Architecture x
2.3.1. FHT PMA Architecture 2.3.2. FGT PMA Architecture
2.3.1. FHT PMA Architecture x
2.3.1.1. FHT Transmitter PMA Architecture 2.3.1.2. FHT Receiver PMA Architecture 2.3.1.3. FHT PMA Loopback Modes
2.3.1.1. FHT Transmitter PMA Architecture x
2.3.1.1.1. FHT Transmitter Buffer and Phase Generator 2.3.1.1.2. FHT Serializer 2.3.1.1.3. FHT Gray-Coder and Pre-Coder 2.3.1.1.4. FHT Data Pattern Generator and Verifier
2.3.1.2. FHT Receiver PMA Architecture x
2.3.1.2.1. FHT Receiver Buffer and Equalizer 2.3.1.2.2. CDR Block 2.3.1.2.3. FHT Deserializer
2.3.2. FGT PMA Architecture x
2.3.2.1. FGT Transmitter PMA Architecture 2.3.2.2. FGT Receiver PMA Architecture 2.3.2.3. FGT PMA Tuning 2.3.2.4. FGT PMA Loopback Modes
2.3.2.1. FGT Transmitter PMA Architecture x
2.3.2.1.1. FGT Transmitter Buffer and Phase Generator 2.3.2.1.2. FGT Serializer 2.3.2.1.3. FGT Gray-Coder and Pre-Coder 2.3.2.1.4. FGT Data Pattern Generator and Verifier
2.3.2.2. FGT Receiver PMA Architecture x
2.3.2.2.1. FGT Receiver Buffer and Equalizer 2.3.2.2.2. Control Unit 2.3.2.2.3. FGT Deserializer
2.4. Clock Architecture x
2.4.1. Reference Clock Network 2.4.2. Datapath Clock Network 2.4.3. System PLL 2.4.4. Datapath Clock Cadences
2.4.1. Reference Clock Network x
2.4.1.1. FHT Reference Clock Network 2.4.1.2. FGT and System PLL Reference Clock Network 2.4.1.3. FGT Primary PLL Configuration
2.4.1.2. FGT and System PLL Reference Clock Network x
2.4.1.2.1. FGT Reference Clock Receiver Analog Front End
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. Unsupported PMA/FEC Modes
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.2.1. Preset IP Parameter Settings
3.3. Configuring the IP x
3.3.1. General and Common Datapath Options 3.3.2. TX Datapath Options 3.3.3. RX Datapath Options 3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options 3.3.5. Avalon® Memory Mapped Interface Options 3.3.6. Register Map IP-XACT Support 3.3.7. Example Design Generation 3.3.8. Analog Parameter Options
3.3.1. General and Common Datapath Options x
3.3.1.1. FGT PMA Configuration Rules for SATA mode 3.3.1.2. FGT PMA Configuration Rules for GPON Mode
3.3.2. TX Datapath Options x
3.3.2.1. TX PMA interface Parameters
3.3.3. RX Datapath Options x
3.3.3.1. RX FGT PMA Interface Options
3.4. Signal and Port Reference x
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals x
3.4.10.1. Number of Datapath Memory Mapped Avalon® Interfaces and Additional Address Bits per Interface
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath x
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations x
3.5.2.1. TX Parallel Data Mapping Information for SATA Protocol Mode for Different Configurations
3.6. Clocking x
3.6.1. Clock Ports 3.6.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.6.4. FGT PMA Fractional Mode 3.6.5. FGT RX CDR Clock Output
3.6.5. FGT RX CDR Clock Output x
3.6.5.1. Dynamically Configure the FGT RX CDR Clock Output
3.7. Custom Cadence Generation Ports and Logic x
3.7.1. Enabling the tx_cadence_slow_clk_locked Port 3.7.2. Rate Match FIFO
3.8. Asserting Reset x
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
3.8.8. Run-time Reset Sequence—TX + RX x
3.8.8.1. Run-time Reset Sequence Approximate Time Durations
3.11. Configuration Registers x
3.11.1. PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. FHT PMA Register Map 3.11.3. FGT PMA Register Map 3.11.4. FEC Register Map 3.11.5. Lane Offset Address 3.11.6. Accessing Configuration Registers
3.11.6. Accessing Configuration Registers x
3.11.6.1. Accessing PMA and FEC Direct PHY Soft CSR Registers 3.11.6.2. Accessing FHT PMA Registers 3.11.6.3. Accessing FGT PMA Registers
3.11.6.2. Accessing FHT PMA Registers x
3.11.6.2.1. FHT PMA Register Address Range 0x40000 to 0x48000 3.11.6.2.2. FHT PMA Register Address Range 0x60000 to 0xF0030 3.11.6.2.3. FHT PMA Register Address 0xFFFFC
3.11.6.3. Accessing FGT PMA Registers x
3.11.6.3.1. FGT PMA Register Address Range 0x40000 to 0x48000 3.11.6.3.2. FGT PMA Register Address Range 0x62000 to 0x62004 3.11.6.3.3. FGT PMA Register Address Range 0x9003C to 0xF0028 3.11.6.3.4. FGT PMA Register Address 0xFFFFC
3.12. Configurable Quartus® Prime Software Settings x
3.12.1. FHT PMA Settings 3.12.2. FGT PMA Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing x
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP
3.13.1. Using Debug Endpoint Interface within the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
3.13.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.13.2. Using JTAG to Avalon® Master Bridge Intel FPGA IP x
3.13.2.1. RTL Connection Example for JTAG to Avalon® Master Bridge Intel IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. FHT PMA 3.14.2. FGT PMA
3.14.1. FHT PMA x
3.14.1.1. Enabling Loopback 3.14.1.2. Enabling the PRBS Generator and Verifier for ES Devices 3.14.1.3. Obtaining BER Values for Production Devices 3.14.1.4. TX Equalizer Settings 3.14.1.5. TX Error Injection 3.14.1.6. RX Reconvergence 3.14.1.7. Preserving Unused Lanes
3.14.2. FGT PMA x
3.14.2.1. Direct Register Method 3.14.2.2. FGT Attribute Access Method
3.14.2.1. Direct Register Method x
3.14.2.1.1. Direct Register Method Examples
3.14.2.2. FGT Attribute Access Method x
3.14.2.2.1. FGT Attribute Access Method Example 1 3.14.2.2.2. FGT Attribute Access Method Example 2 3.14.2.2.3. FGT Attribute Access Method Example 3
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage 4.5. Guidelines for Refclk #i is Active At and After Device Configuration 4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs
4.5. Guidelines for Refclk #i is Active At and After Device Configuration x
4.5.1. Guidelines for System PLL Reference Clock 4.5.2. Guidelines for FGT Reference Clock
4.6. Guidelines for Obtaining the Lock Status and Resetting the FGT and FHT TX PLLs x
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL 4.6.2. How to Read the Real-Time Lock Status of the FHT Lane TX PLL 4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL 4.6.4. How to Reset the FGT TX PLL 4.6.5. How to Reset the FHT Lane TX PLL and Common PLL
4.6.1. How to Read the Real-Time Lock Status of the FGT TX PLL x
4.6.1.1. How to Determine the TX PLL Your FGT Channel is Using
4.6.3. How to Read the Real-Time Lock Status of the FHT Common TX PLL x
4.6.3.1. How to Determine Which Common PLL Your FHT Channel is Using
5. F-Tile PMA/FEC Direct PHY Design Implementation x
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design 5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5.5. Enabling Custom Cadence Generation Ports and Logic 5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP 5.7. Simulating the F-Tile PMA/FEC Direct PHY Design 5.8. F-Tile Interface Planning 5.9. Compiling a F-Tile Design with VHDL Configuration File as the Top Level Module
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP x
5.2.1. Setting General and Common Datapath Options 5.2.2. Setting TX Datapath Options 5.2.3. Setting RX Datapath Options
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design x
5.7.1. PAM4 Encoding Schemes in Simulation
5.8. F-Tile Interface Planning x
5.8.1. F-Tile Interface Planner Usage Example
6. Supported Tools x
6.1. F-Tile Channel Placement Tool 6.2. F-Tile PMA and FEC Direct Port Mapping Calculator 6.3. F-Tile Clocking and Datapath Tool 6.4. F-Tile FGT TX Equalizer Tool 6.5. F-Tile FHT TX Equalizer Tool
7. Debugging F-Tile Transceiver Links x
7.1. F-Tile Transceiver Toolkit GUI 7.2. F-Tile Transceiver Debugging Flow Walkthrough 7.3. Transceiver Toolkit Parameter Settings 7.4. Using F-Tile Multirate IPs with Transceiver Toolkit 7.5. Troubleshooting Common Errors 7.6. Transceiver Toolkit Scripts
7.1. F-Tile Transceiver Toolkit GUI x
7.1.1. Collection View
7.2. F-Tile Transceiver Debugging Flow Walkthrough x
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug 7.2.2. Programming the Design into an Intel FPGA 7.2.3. Loading the Design to the Transceiver Toolkit 7.2.4. Creating Transceiver Links 7.2.5. Running BER Tests 7.2.6. Running Eye Viewer Tests 7.2.7. Running Link Optimization Tests 7.2.8. Checking FEC Statistics 7.2.9. Vertical Bathtub Curve Measurements (VBCM) Data
7.3. Transceiver Toolkit Parameter Settings x
7.3.1. Dashboard
7.4. Using F-Tile Multirate IPs with Transceiver Toolkit x
7.4.1. F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP 7.4.2. F-Tile Ethernet Multirate Intel FPGA IP 7.4.3. Ethernet Subsystem Intel FPGA IP
7.6. Transceiver Toolkit Scripts x
7.6.1. Supported Transceiver Toolkit Scripts 7.6.2. Modifying the Scripts 7.6.3. Script Execution 7.6.4. Example of the Results in Tcl Console
A. Appendix x
A.1. Agilex™ 7 F-Tile OPNs A.2. OSC_CLK_1 QSF Assignment Requirement A.3. FGT Internal Serial Loopback Calibration Sequence for RX Manual Adaptation A.4. Transceiver Toolkit Helper Script A.5. F-Tile Tuning Guidelines
A.4. Transceiver Toolkit Helper Script x
A.4.1. Introduction A.4.2. Executing the Script
A.5. F-Tile Tuning Guidelines x
A.5.1. Introduction A.5.2. Equalization Techniques Overview A.5.3. Equalization Recommendations for F-Tile FGT PMA Transceivers A.5.4. F-Tile FGT PMA Tuning Guide A.5.5. Equalization Recommendations for F-Tile FHT PMA Transceivers A.5.6. F-Tile FHT PMA Tuning Guide A.5.7. Appendix
A.5.1. Introduction x
A.5.1.1. F-Tile PMA Overview A.5.1.2. Equalization Techniques Overview
A.5.1.2. Equalization Techniques Overview x
A.5.1.2.1. FGT Transmitter Equalization Tuning Taps A.5.1.2.2. FGT Receiver Adaptation A.5.1.2.3. FGT Media Selection A.5.1.2.4. FHT Transmitter Equalization Tuning Taps
A.5.3. Equalization Recommendations for F-Tile FGT PMA Transceivers x
A.5.3.1. F-Tile FGT Transmitter Equalization Parameters A.5.3.2. F-Tile FGT Transmitter Setting Recommendations A.5.3.3. F-Tile FGT Receiver Equalization Parameters A.5.3.4. F-Tile FGT Receiver Setting Recommendations
A.5.4. F-Tile FGT PMA Tuning Guide x
A.5.4.1. F-Tile FGT NRZ Tuning Flow A.5.4.2. F-Tile FGT Hardware Setup A.5.4.3. F-Tile FGT Tuning Examples
A.5.4.3. F-Tile FGT Tuning Examples x
A.5.4.3.1. Example 1 : F-Tile FGT 25 Gbps NRZ Design A.5.4.3.2. Example 2 : F-Tile FGT 58 Gbps PAM4 and FEC Design A.5.4.3.3. Example 3 : F-Tile FGT 5 Gbps NRZ Design
A.5.5. Equalization Recommendations for F-Tile FHT PMA Transceivers x
A.5.5.1. F-Tile FHT Transmitter Equalization Parameters A.5.5.2. F-Tile FHT Transmitter Setting Recommendations A.5.5.3. F-Tile FHT Receiver Equalization Parameters
A.5.6. F-Tile FHT PMA Tuning Guide x
A.5.6.1. F-Tile FHT Tuning Flow A.5.6.2. F-Tile FHT Hardware Setup A.5.6.3. F-Tile FHT Tuning Examples
A.5.6.3. F-Tile FHT Tuning Examples x
A.5.6.3.1. Example 1 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.5.6.3.2. Example 2 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.5.6.3.3. Example 3 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.5.6.3.4. Example 4 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.5.6.3.5. Example 5 : F-Tile FHT 106 Gbps PAM4 Design (Short Reach) A.5.6.3.6. Example 6 : F-Tile FHT 106 Gbps PAM4 Design (Long Reach) A.5.6.3.7. Example 7 : F-Tile FHT 25 Gbps NRZ Design (Short Reach) A.5.6.3.8. Example 8 : F-Tile FHT 25 Gbps NRZ Design (Long Reach) A.5.6.3.9. Example 9 : F-Tile FHT 50 Gbps PAM4 Design (Short Reach) A.5.6.3.10. Example 10 : F-Tile FHT 50 Gbps PAM4 Design (Long Reach)
A.5.7. Appendix x
A.5.7.1. FCI Backplane Design A.5.7.2. F-Tile FGT Tuning Script A.5.7.3. F-Tile FGT Attribute Access Sequence
1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix

A.5.7.3. F-Tile FGT Attribute Access Sequence

The following tables describe the various FGT attribute access sequences required for FGT tuning.
Table 139.  FGT Attribute Access Sequence for FOM, VGA, CTLE
Opcode Field[7:0] Data Field[31:16] Description Address 58 Transaction Type Value (32-bit)
0x94 0x6000 FOM 0x9003C Write 0x60008094
0x90040 Read 0x60008094
0x9003C Write 0x60000094
0x90040 Read 0x60000094
0x94 0x4000 VGA 0x9003C Write 0x40008094
0x90040 Read 0x40008094
0x9003C Write 0x40000094
0x90040 Read 0x40000094
0x94 0x4001 CTLE 0x9003C Write 0x40018094
0x90040 Read 0x40018094
0x9003C Write 0x40010094
0x90040 Read 0x40010094
Table 140.  FGT Attribute Access Sequence for BER Measurement
Opcode Field[7:0] Data Field[31:16] Description Address58 Transaction Type Value (32-bit)
0xD 0x0 Poll for RX READY 0x9003C Write 0x800D
0x90040 Read 0x1800D 59
0x9003C Write 0x000D
0x90040 Read 0x000D
0x41 0x30C

Set PRBS pattern31 60

0x9003C Write 0x30CA041
0x90040 Read 0x30CA041
0x9003C Write 0x30CA041
0x90040 Read 0x30C2041
0x45 0x14 Set up BER test 0x9003C Write 0x14A045
0x90040 Read 0x14A045
0x9003C Write 0x142045
0x90040 Read 0x142045
0x0F 0x20 Start test 0x9003C Write 0x20A00F
0x90040 Read 0x20A00F
0x9003C Write 0x20200F
0x90040 Read 0x20200F
0x49 0x0 Check test status (GET) 0x9003C Write 0x8049
0x90040 Read 0x1008049 (test running)
0x9003C Write 0x0049
0x90040 Read 0x0049
0x0F 0x21 Stop test 0x9003C Write 0x21A00F
0x90040 Read 0x21A00F
0x9003C Write 0x21200F
0x90040 Read 0x21200F
0x49 0x0 Check test complete with success 0x9003C Write 0x8049
0x90040 Read 0x3008049 (complete with success)
0x9003C Write 0x00049
0x90040 Read 0x00049
0x4A 0x0 Get test results for LSB 12 bits 0x9003C Write 0x0000804A
0x90040 Read 0x(Read 12bits)804A
0x9003C Write 0x0000004A
0x90040 Read 0x0000004A
0x4B 0x0 Get test results for middle 16 bits 0x9003C Write 0x0000804B
0x90040 Read 0x(Read 16bits)804B
0x9003C Write 0x0000004B
0x90040 Read 0x0000004B
0X4C 0x0 Get test results for MSB 4 bits 0x9003C Write 0x0000804C
0x90040 Read 0x(Read 4bits)804C
0x9003C Write 0x0000004C
0x90040 Read 0x0000004C
Table 141.  FGT Attribute Access Sequence for Eye Height Measurement
Opcode Field[7:0] Data Field[31:16] Description Address58 Transaction Type Value (32-bit)
0xD 0x0 Poll for RX READY 0x9003C Write 0x0000800D
0x90040 Read 0x0001800D 61
0x9003C Write 0x0000000D
0x90040 Read 0x0000000D
0x45 0x7 EHM test 0x9003C Write 0x007A045
0x90040 Read 0x007A045
0x9003C Write 0x0072045
0x90040 Read 0x0072045
0x91 0x5 Clear previous configuration 0x9003C Write 0x0005A091
0x90040 Read 0x0005A091
0x9003C Write 0x00052091
0x90040 Read 0x00052091
0x48

0xDB

0xC9

0xFF

0xED

Refer to ttk_helper_ftile.tcl

Set basic measurement configuration 0x9003C Write 0x(varies)A04862
0x90040 Read 0x(varies)A04862
0x9003C Write 0x(varies)204862
0x90040 Read 0x(varies)204862
0x48

0xC6F

0xF391 for BER = 1E-6

Refer to ttk_helper_ftile.tcl

Set event rate lsb1 0x9003C Write 0x(varies)A048
0x90040 Read 0x(varies)A04862
0x9003C Write 0x(varies)204862
0x90040 Read 0x(varies)204862
0x48

0x1

0xFFFE for BER = 1E-6

Refer to ttk_helper_ftile.tcl

Set event rate lsb2 0x9003C Write 0x(varies)A04862
0x90040 Read 0x(varies)A04862
0x9003C Write 0x(varies)204862
0x90040 Read 0x(varies)204862
0x48

0x100

0xFF for BER = 1E-6

Refer to ttk_helper_ftile.tcl

Set event rate msb 0x9003C Write 0x(varies)A04862
0x90040 Read 0x(varies)A04862
0x9003C Write 0x(varies)204862
0x90040 Read 0x(varies)204862
0xF 0x20 Start test 0x9003C Write 0x20A00F
0x90040 Read 0x20A00F
0x9003C Write 0x20200F
0x90040 Read 0x20200F
0x49 0x0 Check test complete with success 0x9003C Write 0x00008049
0x90040 Read

0x03008049

(complete with success)
0x9003C Write 0x00000049
0x90040 Read 0x00000049
0x0F 0x21 Stop test 0x9003C Write 0x0021A00F
0x90040 Read 0x0021A00F
0x9003C Write 0x0021200F
0x90040 Read 0x0021200F
0x4A 0x0

Get test results

LSB 12bits

 0x9003C Write 0x0000804A
0x90040 Read 0x(Read12bits)804A
0x9003C Write 0x0000004A
0x90040 Read 0x0000004A
Table 142.  FGT Attribute Access Sequence for VSR High Loss Between and Low Loss
Opcode Field[7:0] Data Field[31:16] Description Address58 Transaction Type Value (32-bit)
0x64 0x15 Set to VSR High Loss 0x9003C Write 0x15A064
0x90040 Read 0x15A064
0x9003C Write 0x152064
0x90040 Read 0x152064
0x64 0x14 Set to VSR Low Loss 0x9003C Write 0x14A064
0x90040 Read 0x14A064
0x9003C Write 0x142064
0x90040 Read 0x142064
0x64 0x10 Set to SR/MR/LR (default) 0x9003C Write 0x00A064
0x90040 Read 0x00A064
0x9003C Write 0x002064
0x90040 Read 0x002064
58 Registers are for channel 0. Refer to FGT Attribute Access Method for other channels.
59
  • Physical lane 0: 0x0001800D
  • Physical lane 1: 0x0002800D
  • Physical lane 2: 0x0004800D
  • Physical lane 3: 0x0008800D
60 For other PRBS patterns refer to the FGT Attribute Access Method section.
61
  • Physical lane 0: 0x0001800D
  • Physical lane 1: 0x0002800D
  • Physical lane 2: 0x0004800D
  • Physical lane 3: 0x0008800D
62 Varies based on BER settings. Refer to ttk_helper_ftile.tcl.
Level Two Title